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MB90F347C

Fujitsu Media Devices
Part Number MB90F347C
Manufacturer Fujitsu Media Devices
Description 16-bit Proprietary Microcontroller
Published Oct 1, 2014
Detailed Description FUJITSU SEMICONDUCTOR DATA SHEET DS07-13730-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90340 Series MB90F...
Datasheet PDF File MB90F347C PDF File

MB90F347C
MB90F347C

Overview
FUJITSU SEMICONDUCTOR DATA SHEET DS07-13730-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90340 Series MB90F342/C(S), MB90F343/C(S), MB90F345/C(S), MB90F346/C(S), MB90F347/C(S), MB90F349/C(S), MB90341/C(S), MB90342/C(S), MB90346/C(S), MB90347/C(S), MB90348/C(S), MB90349/C(S), MB90V340(S) s DESCRIPTION The MB90340-series with up to 2 FULL-CAN* interfaces and FLASH ROM is especially designed for automotive and industrial applications.
Its main feature are the on-board CAN Interfaces, which conform to V2.
0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach.
With the new 0.
35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory up to 512 Kbytes.
An internal voltage booster removes the necessity for a second programming voltage.
An on board voltage regulator provides 3 V to the internal MCU core.
This creates a major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock.
The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free running timers.
4 UARTs constitute additional functionality for communication purposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH Note : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
s PACKAGES 100-pin Plastic QFP 100-pin Plastic LQFP (FPT-100P-M06) (FPT-100P-M05) MB90340 Series s FEATURES • Clock • Built-in PLL clock frequency multiplication circuit • Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided two) is allowed.
(devices without Ssuffix only) • Minimum ex...


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