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SN74LS273

Motorola
Part Number SN74LS273
Manufacturer Motorola
Description OCTAL D FLIP-FLOP
Published Oct 12, 2014
Detailed Description OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Fl...
Datasheet PDF File SN74LS273 PDF File

SN74LS273
SN74LS273

Overview
OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register.
The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset.
This device is supplied in a 20-pin package featuring 0.
3 inch lead spacing.
SN54/74LS273 • • • • 8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 20 Q7 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11 OCTAL D FLIP-FLOP WITH CLEAR LOW POWER SCHOTTKY 20 1 J SUFFIX CERAMIC CASE 732-03 1 MR 2 Q0 3 D0 4 D1 5 Q1 6 Q2 7 D2 8 D3 9 Q3 10 GND 20 1 N SUFFIX PLASTIC CASE 738-03 PIN NAMES LOADING (Note a) HIGH LOW 0.
25 U.
L.
0.
25 U.
L.
0.
25 U.
L.
5 (2.
5) U.
L.
CP D0 – D7 MR Q0 – Q7 Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs (Note b) 0.
5 U.
L.
0.
5 U.
L.
0.
5 U.
L.
10 U.
L.
20 1 DW SUFFIX SOIC CASE 751D-03 NOTES: a) 1 TTL Unit Load (U.
L.
) = 40 µA HIGH/1.
6 mA LOW.
b) The Output LOW drive factor is 2.
5 U.
L.
for Military (54) and 5 U.
L.
for Commercial (74) Temperature Ranges.
ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC TRUTH TABLE MR L H H CP X Dx X H L Qx L H L H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM 11 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 CP CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q 1 MR VCC = PIN 20 GND = PIN 10 = PIN NUMBERS Q0 2 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 Q7 19 FAST AND LS TTL DATA 5-447 SN54/74LS273 FUNCTIONAL DESCRIPTION The SN54 / 74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset.
When the MR input is LOW, the Q outputs are LOW, independent of the other inputs.
Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input.
GUARAN...


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