R5F51103ADFM Datasheet

R5F51103ADFM 32 MHz 32-bit RX MCUs

CPU CPU  Maximum operating frequency: 32 MHz  32-bit RX CPU  Minimum instruction execution time: One instruction per one clock cycle  Address space: 4-Gbyte linear  Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register  Basic.

Features

■ 32-bit RX CPU core
 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz
 Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations
 Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle)
 Fast interrupt
 CISC Harvard architecture with five-stage pipeline
 Variable-length instruction format, ultra-compact code
 On-chip debugging circuit
■ Low power consumption functions
 Operation from a single 1.8 to 3.6 V supply
 Three low power modes
 Supply current .