MTD20N03HL. 20N03HL Datasheet

20N03HL Datasheet PDF

Part 20N03HL
Description MTD20N03HL
Feature MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTD20N03HDL/D Designer's HDTMOS E-F.
Manufacture Motorola
Datasheet
Download 20N03HL Datasheet




20N03HL
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD20N03HDL/D
Designer's
Data Sheet
HDTMOS E-FET .
High Density Power FET
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
www.DataSheet4cUo.nctormols, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
G
D
S
MTD20N03HDL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
20 AMPERES
30 VOLTS
RDS(on) = 0.035 OHM
CASE 369A–13, Style 2
DPAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 M)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
VDSS 30 Vdc
VDGR 30 Vdc
VGS
±15 Vdc
VGSM ± 20 Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
ID 20 Adc
ID 16
IDM 60 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size
PD 74 Watts
0.6 W/°C
1.75
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 )
EAS 200 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
RθJC
RθJA
RθJA
1.67 °C/W
100
71.4
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET, and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
© MMoototororloa,laIncT.M19O95S Power MOSFET Transistor Device Data
1



20N03HL
MTD20N03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
(Cpk 2.0) (3) V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current
(VGS = ±15 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
www.DataSheet4U.com
Static Drain–to–Source On–Resistance
(VGS = 4.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 10 Adc)
(Cpk 2.0) (3)
(Cpk 2.0) (3)
Drain–to–Source On–Voltage (VGS = 5.0 Vdc)
(ID = 20 Adc)
(ID = 10 Adc, TJ = 125°C)
Forward Transconductance
(VDS = 5.0 Vdc, ID = 10 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDD = 15 Vdc, ID = 20 Adc,
VGS = 5.0 Vdc,
RG = 9.1 )
(VDS = 24 Vdc, ID = 20 Adc,
VGS = 5.0 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(Cpk 2.0) (3)
(IS = 20 Adc, VGS = 0 Vdc)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
IDSS
IGSS
VGS(th)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
Reverse Recovery Time
(See Figure 15)
(IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk = Absolute Value of Spec (Spec–AVG/3.516 µA).
trr
ta
tb
QRR
LD
LS
Min
30
1.0
10
Typ Max Unit
Vdc
——
43 — mV/°C
µAdc
— 10
— 100
nAdc
— 100
1.5
5.0
0.034
0.030
0.55
13
2.0
0.040
0.035
0.8
0.7
Vdc
mV/°C
Ohm
Vdc
mhos
880 1260
300 420
80 112
pF
13 15.8
212 238
37 30
84 96
13.4 18.9
3.0 —
7.3 —
6.0 —
ns
nC
Vdc
0.95 1.1
0.87 —
33 — ns
23 —
10 —
33 — µC
nH
4.5 —
nH
7.5 —
2 Motorola TMOS Power MOSFET Transistor Device Data


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)