54SXxx Datasheet PDF
FPGAs
- 54SXxx | Actel
- FPGAs
-
v3.1
54SX Family FPGAs
Le a di ng E dg e P er f or m a nc e F ea t u r es
• 320 MHz Internal Performance • 3.7 ns Clock-to-Out (Pin-to-Pin) • 0.1 ns Input Set-Up • 0.25 ns Clock Skew
Sp e ci f ic at ion s
• 66 MHz PCI • CPLD and FPGA Integration • Single Chip Solution • 100% Resource Utilization with 100% Pin Locking • 3.3V Operation with 5.0V Input Tolerance • Very Low Power Consumption • Deterministic, User-Controllable Timing • Unique In-Sy.
- 54SXxx | Actel
- General Purpose SDRAM Controller
-
v2.0
General-Purpose SDRAM Controller
SD R A M Co n t r o l l er Fu nc t i o na l D es cr i p t i o n
The general-purpose SDRAM controller is designed to provide simplified control of many different sizes of SDRAMs. The controller architecture provides control for data bursts by linearly incrementing the address. The user starts a burst at a specified address and the burst continues until the user terminates it.
SD R A M Co n t r o l l er Si g .
- 54SXxx | Actel
- General Purpose SDRAM Controller
- v2.0
General-Purpose SDRAM Controller
SD R A M Co n t r o l l er Fu nc t i o na l D es cr i p t i o.
- v2.0
General-Purpose SDRAM Controller
SD R A M Co n t r o l l er Fu nc t i o na l D es cr i p t i o n
The general-purpose SDRAM controller is designed to provide simplified control of many different sizes of SDRAMs. The controller architecture provides control for data bursts by linearly incrementing the address. The user starts a burst at a specified address and the burst continues until the user terminates it.
SD R A M Co n t r o l l er Si g .
- 54SXxx | Actel
- FPGAs
- v3.1
54SX Family FPGAs
Le a di ng E dg e P er f or m a nc e F ea t u r es
• 320 MHz Internal Perfo.
- v3.1
54SX Family FPGAs
Le a di ng E dg e P er f or m a nc e F ea t u r es
• 320 MHz Internal Performance • 3.7 ns Clock-to-Out (Pin-to-Pin) • 0.1 ns Input Set-Up • 0.25 ns Clock Skew
Sp e ci f ic at ion s
• 66 MHz PCI • CPLD and FPGA Integration • Single Chip Solution • 100% Resource Utilization with 100% Pin Locking • 3.3V Operation with 5.0V Input Tolerance • Very Low Power Consumption • Deterministic, User-Controllable Timing • Unique In-Sy.
- 54SXxxA | Actel
- SX-A Family FPGAs
- v5.1
SX-A Family FPGAs
Leading-Edge Performance
• • 250 MHz System Performance 350 MHz Internal Per.
- v5.1
SX-A Family FPGAs
Leading-Edge Performance
• • 250 MHz System Performance 350 MHz Internal Performance • • • • • • • • • •
™
Specifications
• • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops 0.22 µ / 0.25 µ CMOS Process Technology
Features
• • • • Hot-Swap Compliant I/Os Power-Up/Down Friendly (No Sequencing Required for Supply Voltages) 66 MHz PCI Compliant Nonvolatile,.