Clock Generator. 5P49V5935 Datasheet

5P49V5935 Datasheet PDF


Part Number

5P49V5935

Description

Programmable Clock Generator

Manufacture

Renesas

Total Page 30 Pages
Datasheet
Download 5P49V5935 Datasheet



5P49V5935
Programmable Clock Generator
5P49V5935
DATASHEET
Description
The 5P49V5935 is a programmable clock generator intended
for high-performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDT’s fifth generation of programmable clock
technology (VersaClock® 5).
The 5P49V5935 by default uses an integrated 25MHz crystal
as input reference. It also has a redundant external clock
input. A glitchless manual switchover functions allows
selection of either one as mentioned above as input reference
during normal operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
NC
NC
VDDA
CLKSEL
1 24 23
22
21
20
19
18
2 17
3 16
4
EPAD
15
5 14
6 13
7 8 9 10 11 12
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
Features
Generates up to four independent output frequencies
High-performance, low phase noise PLL, < 0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1GbE and 10GbE
Four fractional output dividers (FODs)
Independent spread spectrum capability on each output
pair
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
One reference LVCMOS output clock
Four universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os: LVPECL, LVDS and HCSL
Input frequency ranges:
– LVDS, LVPECL, HCSL differential clock input (CLKIN,
CLKINB) – 1MHz to 350MHz
Output frequency ranges:
– LVCMOS clock outputs: 1MHz to 200MHz
– LVDS, LVPECL, HCSL differential clock outputs: 1MHz
to 350MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
4 x 4 mm 24-LGA package
-40° to +85°C industrial temperature operation
4 × 4 mm 24-LGA
5P49V5935 NOVEMBER 1, 2017
1 ©2017 Integrated Device Technology, Inc.

5P49V5935
5P49V5935 DATASHEET
Functional Block Diagram
OSC
25MHz
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
VDDA
VDDD
OTP
and
Control Logic
PLL
Applications
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1GbE and 10GbE
FOD1
FOD2
FOD3
FOD4
PROGRAMMABLE CLOCK GENERATOR
2
VDDO0
OUT0_SEL_I2CB
VDDO1
OUT1
OUT1B
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
VDDO4
OUT4
OUT4B
NOVEMBER 1, 2017




@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)