Register. 74ACT399 Datasheet

74ACT399 Datasheet PDF

Part 74ACT399
Description Quad 2-Port Register
Feature 74AC399 • 74ACT399 Quad 2-Port Register June 1988 Revised October 2000 74AC399 • 74ACT399 Quad 2-P.
Manufacture Fairchild Semiconductor
Datasheet
Download 74ACT399 Datasheet





74ACT399
June 1988
Revised October 2000
74AC399 74ACT399
Quad 2-Port Register
General Description
The AC/ACT399 is the logical equivalent of a quad 2-input
multiplexer feeding into four edge-triggered flip-flops. A
common Select input determines which of the two 4-bit
words is accepted. The selected data enters the flip-flop on
the rising edge of the clock.
Features
s ICC reduced by 50%
s Select inputs from two data sources
s Fully positive edge-triggered operation
s Outputs source/sink 24 mA
s AC/ACT399 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC399SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74AC399PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT399SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74ACT399SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT399MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT399PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
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Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
S
CP
I0aI0d
I1aI1d
QaQd
Description
Common Select Input
Clock Pulse Input
Data Inputs from Source 0
Data Inputs from Source 1
Register True Outputs
FACTis a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS009789
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74ACT399
Functional Description
The AC/ACT399 is a high-speed quad 2-port register. It
selects four bits of data from either of two sources (Ports)
under control of a common Select input (S). The selected
data is transferred to a 4-bit output register synchronous
with the LOW-to-HIGH transition of the Clock input (CP).
The 4-bit D-type output register is fully edge-triggered. The
Data inputs (I0x, I1x) and Select input (S) must be stable
only a setup time prior to and hold time after the LOW-to-
HIGH transition of the Clock input for predictable operation.
Logic Diagram
Function Table
Inputs
S I0
I1
LL
X
LH
X
HX
L
HX
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
CP




Outputs
QQ
LH
HL
LH
HL
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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