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74F373 LATCHES Datasheet PDFOCTAL TRANSPARENT D-TYPE LATCHES OCTAL TRANSPARENT D-TYPE LATCHES |
| Part Number | 74F373 |
|---|---|
| Description | OCTAL TRANSPARENT D-TYPE LATCHES |
| Feature | SN54F373, SN74F373 OCTAL TRANSPARENT D-T YPE LATCHES
WITH 3-STATE OUTPUTS
SDFS07 6A – D2932, MARCH 1987 – REVISED OC TOBER 1993
• Eight Latches in a Sing le Package • 3-State Bus-Driving True Outputs • Full Parallel Access for L oading • Buffered Control Inputs • Package Options Include Plastic Small-O utline (SOIC) and Shrink Small-Outline (SSOP) Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs descripti on These 8-bit latches feature 3-state outputs designed specifically for drivi ng highly capacitive or relatively low- impedance loads. They are particularly suitable for implementing bu . |
| Manufacture | Texas Instruments |
| Datasheet |
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| Part Number | 74F373 |
|---|---|
| Description | Octal Transparent Latch |
| Feature | 54F 74F373 Octal Transparent Latch with TRI-STATE Outputs May 1995 54F 74F373 Octal Transparent Latch with TRI-STATE Outputs General Description The ’F37 3 consists of eight latches with TRI-ST ATE outputs for bus organized system ap plications The flip-flops appear transp arent to the data when Latch Enable (LE ) is HIGH When LE is LOW the data that meets the setup times is latched Data a ppears on the bus when the Output Enabl e (OE) is LOW When OE is HIGH the bus o utput is in the high impedance state F eatures Y Y Y Eight latches in a singl e package TRI-STATE outputs for bus int erfacing Guarant . |
| Manufacture | National |
| Datasheet |
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| Part Number | 74F373 |
|---|---|
| Description | Octal Transparent Latch |
| Feature | www. DataSheet4U. com 74F373 Octal Transp arent Latch with 3-STATE Outputs May 1 988 Revised September 2000 74F373 Octa l Transparent Latch with 3-STATE Output s General Description The 74F373 consis ts of eight latches with 3-STATE output s for bus organized system applications . The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH . When LE is LOW, the data that meets t he setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. Featu res s Eight latches in a single package s 3-STATE out . |
| Manufacture | Fairchild |
| Datasheet |
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