| DatasheetsPDF.com |
74HC595 Register Datasheet PDF8-Bit Serial-Input/Serial or Parallel-Output Shift Register 8-Bit Serial-Input/Serial or Parallel-Output Shift Register |
| Part Number | 74HC595 |
|---|---|
| Description | 8-Bit Serial-Input/Serial or Parallel-Output Shift Register |
| Feature | 74HC595
8−Bit Serial−Input/Serial o r
Parallel−Output Shift
Register with Latched
3−State Outputs
High−Perfo rmance Silicon−Gate CMOS
The 74HC595 consists of an 8−bit shift register a nd an 8−bit D−type latch with three −state parallel outputs. The shift re gister accepts serial data and provides a serial output. The shift register al so provides parallel data to the 8−bi t latch. The shift register and latch h ave independent clock inputs. This devi ce also has an asynchronous reset for t he shift register. The HC595 directly i nterfaces with the SPI serial data port on CMOS MPUs and MCUs. Features • O . |
| Manufacture | ON Semiconductor |
| Datasheet |
|
|
| Part Number | 74HC595 |
|---|---|
| Description | 8-bit serial-in serial or parallel-out shift register |
| Feature | 74HC595; 74HCT595
8-bit serial-in, seri al or parallel-out shift register with output
latches; 3-state
Rev. 9 — 28 February 2017 Product data sheet 1 G eneral description The 74HC595; 74HCT59 5 is an 8-bit serial-in/serial or paral lel-out shift register with a storage r egister and 3-state outputs. Both the s hift and storage register have separate clocks. The device features a serial i nput (DS) and a serial output (Q7S) to enable cascading and an asynchronous re set MR input. A LOW on MR will reset th e shift register. Data is shifted on th e LOW-to-HIGH transitions of the SHCP i nput. The data i . |
| Manufacture | NXP |
| Datasheet |
 |
| Part Number | 74HC595 |
|---|---|
| Description | 8-BIT SHIFT REGISTER |
| Feature | 74HC595
8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER
Description
The 74HC59 5 is an high speed CMOS device. An eigh t bit shift register accpets data from the serial input (DS) on each positive transition of the shift register clock (SHCP). When asserted low the reset fun ction ( ) sets all shift register value s to zero and is indepent of all clocks . Data from the input serial shift regi ster is placed in the output register w ith a rising pulse on the storages resi ster clock (STCP). With the output enab le ( E asserted low the 3-state outputs Q0-Q7 become active and present th All registers cap . |
| Manufacture | Diodes |
| Datasheet |
 |
|
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact) |