• One LVPECL output pair
• Two selectable differential LVPECL clock inputs
• PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML
• Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx
• Part-to-part skew: 150p...
853S01 PDF File
