Memory. AT25DQ161 Datasheet

AT25DQ161 Datasheet PDF

Part AT25DQ161
Description 16-Megabit 2.7-volt Minimum SPI Serial Flash Memory
Feature AT25DQ161; Features • Single 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible – Supports SPI M.
Manufacture Atmel Corporation
Datasheet
Download AT25DQ161 Datasheet




AT25DQ161
Features
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS Operation
– Supports Dual- and Quad-Input Program
– Supports Dual- and Quad-Output Read
Very High Operating Frequencies
– 100 MHz for RapidS
– 85 MHz for SPI
– Clock-to-Output (tV) of 5 ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– 32 Sectors of 64-Kbytes Each
Hardware Controlled Locking of Protected Sectors via WP Pin
Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
128-Byte Programmable OTP Security Register
Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
– 1.0 ms Typical Page Program (256 Bytes) Time
– 50 ms Typical 4-Kbyte Block Erase Time
– 250 ms Typical 32-Kbyte Block Erase Time
– 400 ms Typical 64-Kbyte Block Erase Time
Program and Erase Suspend/Resume
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 5 mA Active Read Current (Typical at 20 MHz)
– 5 µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
16-Megabit
2.7-volt
Minimum
SPI Serial Flash
Memory with
Dual-I/O and
Quad-I/O
Support
AT25DQ161
Preliminary
8671A–DFLASH–07/09
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AT25DQ161
1. Description
The AT25DQ161 is a serial interface Flash memory device designed for use in a wide variety of
high-volume consumer based applications in which program code is shadowed from Flash
memory into embedded or external RAM for execution. The flexible erase architecture of the
AT25DQ161, with its erase granularity as small as 4-Kbytes, makes it ideal for data storage as
well, eliminating the need for additional data storage EEPROM devices.
The physical sectoring and the erase block sizes of the AT25DQ161 have been optimized to
meet the needs of today's code and data storage applications. By optimizing the size of the
physical sectors and erase blocks, the memory space can be used much more efficiently.
Because certain code modules and data storage segments must reside by themselves in their
own protected sectors, the wasted and unused memory space that occurs with large sectored
and large block erase Flash m emory devices can be greatly reduced. This increased memory
space efficiency allows additional code routines and data storage segments to be added while
still maintaining the same overall device density.
The AT25 DQ161 also offers a sop histica ted me thod for protecting individual sectors ag ainst
erroneous or malicious program and erase operations. By providing the ability to individually pro-
tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applica-
tion s whe re p rogram co de is pa tch ed o r up dat ed on a su bro utine or mo dule basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments. In addition to individual sector protection capabili-
ties, the AT25DQ161 incorporates Global Protect and Global Unprotect features that allow the
entire m emory array to b e eithe r protected or unprotected all at on ce. This red uces overhead
during the manufacturing process since sectors do not have to be unprotected one-by-one prior
to initial programming.
To take code and data protection to the next level, the AT25DQ161 incorporates a sector lock-
down mechanism that allows any combination of individual 64-Kbyte sectors to be locked down
and become permanently read-only. This addresses the need of certain secure applications that
require p ortions of the Flash m emory ar ray to be pe rman ently p rotected against malicio us
attempts at altering program code, data modules, security information, or encryption/decryption
algorithms, ke ys, an d routines. The device also contains a specialized OTP ( One-Time Pro-
gr amm able) Se curity Register th at can be used for purpo ses such as un ique device
serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3-vo lt syste ms, the AT2 5DQ161 sup ports read, pr ogram, and
erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for
programming and erasing.
2 AT25DQ161 [Preliminary]
8671A–DFLASH–07/09



AT25DQ161
AT25DQ161 [Preliminary]
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Symbol
CS
SCK
SI (I/O0)
SO (I/O1)
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted,
the device will be deselected and normally be placed in standby mode (not Deep Power-
Down mode), and the SO pin will be in a high-impedance state. When the device is
deselected, data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control
the flow of data to and from the device. Command, address, and input data present on
the SI pin or I/O pins is always latched in on the rising edge of SCK, while output data on
the SO pin or I/O pins is always clocked out on the falling edge of SCK.
SERIAL INPUT (I/O0): The SI pin is used to shift data into the device. The SI pin is used
for all data input including command and address sequences. Data on the SI pin is
always latched in on the rising edge of SCK.
With the Dual-Input and Quad-Input Byte/Page Program commands, the SI pin is used as
an input pin (I/O0) in conjunction with other pins to allow two bits (on I/O1-0) or four bits (on
I/O3-0) of data to be clocked in on every rising edge of SCK. With the Dual-Output and
Quad-Output Read Array commands, the SI pin becomes an output pin (I/O0) and, along
with other pins, allows two bits (on I/O1-0) or four bits (on I/O3-0) of data to be clocked out
on every falling edge of SCK. To maintain consistency with SPI nomenclature, the SI
(I/O0) pin will be referenced as SI throughout the document with exception to sections
dealing with the Dual-Input and Quad-Input Byte/Page Program commands as well as the
Dual-Output and Quad-Output Read Array commands in which it will be referenced as
I/O0.
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
SERIAL OUTPUT (I/O1): The SO pin is used to shift data out from the device. Data on
the SO pin is always clocked out on the falling edge of SCK.
With the Dual-Input and Quad-Input Byte/Page Program commands, the SO pin becomes
an input pin (I/O1) and, along with other pins, allows two bits (on I/O1-0) or four bits (on
I/O3-0) of data to be clocked in on every rising edge of SCK. With the Dual-Output and
Quad-Output Read Array commands, the SO pin is used as an output pin (I/O1) in
conjunction with other pins to allow two bits (on I/O1-0) or four bits (on I/O3-0) of data to be
clocked out on every falling edge of SCK. To maintain consistency with SPI
nomenclature, the SO (I/O1) pin will be referenced as SO throughout the document with
exception to sections dealing with the Dual-Input and Quad-Input Byte/Page Program
commands as well as the Dual-Output and Quad-Output Read Array commands in which
it will be referenced as I/O1.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
Asserted
State
Low
-
-
-
Type
Input
Input
Input/Output
Input/Output
8671A–DFLASH–07/09
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