Features
80C51 Core Architecture 256 Bytes of On-chip RAM 1 KB of On-chip XRAM 32 KB of On-chip Flash Memory
– Data Retention: 10 Years at 85°C Read/Write Cycle: 10K
2 KB of On-chip Flash for Bootloader 2 KB of On-chip EEPROM
Read/Write Cycle: 100K 14-sources 4-level Interrupts Three 16-bit Timers/Counters Full Duplex UART Compatible 80C51 ...
