Processor. AT91CAP9SC500A Datasheet

AT91CAP9SC500A Datasheet PDF

Part AT91CAP9SC500A
Description (AT91CAP9SC250A / AT91CAP9SC500A) Customizable Microcontroller Processor
Feature Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction.
Manufacture ATMEL Corporation
Download AT91CAP9SC500A Datasheet Features • Incorporates the ARM926EJ-S™ AT91CAP9SC500A Datasheet

Incorporates the ARM926EJ-SARM® Thumb® Processor
– DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 220 MIPS at 200 MHz
– Memory Management Unit
– EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support
Additional Embedded Memories
– One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed
– One 32 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed
External Bus Interface (EBI)
– EBI Supports Mobile DDR, SDRAM, Low Power SDRAM, Static Memory,
Synchronous CellularRAM, ECC-enabled NAND Flash and CompactFlash®
Metal Programmable (MP) Block
– 500,000 Gates/250,000 Gates Metal Programmable Logic (through 5 Metal Layers)
for AT91CAP9SC500A/AT91CAP9SC250A Respectively
– Ten 512 x 36-bit Dual Port RAMs
– Eight 512 x 72-bit Single Port RAMs
– High Connectivity for Up to Three AHB Masters and Four AHB Slaves
– Up to Seven AIC Interrupt Inputs
– Up to Four DMA Hardware Handshake Interfaces
– Delay Lines for Double Data Rate Interface
– UTMI+ Full Connection
– Up to 77 Dedicated I/Os
LCD Controller
– Supports Passive or Active Displays
– Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Wider
Screen Buffers
Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
USB 2.0 Full Speed (12 Mbits per second) OHCI Host Double Port
– Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
USB 2.0 High Speed (480 Mbits per second) Device Port
– On-chip Transceiver, 4 Kbyte Configurable Integrated DPRAM
– Integrated FIFOs and Dedicated DMA Channels
– Integrated UTMI+ Physical Interface
Ethernet MAC 10/100 Base T
– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
Multi-Layer Bus Matrix
– Twelve 32-bit-layer Matrix, Allowing a Maximum of 38.4 Gbps of On-chip Bus
Bandwidth at Maximum 100 MHz System Clock Speed
– Boot Mode Select Option, Remap Command
Fully-featured System Controller, Including
– Reset Controller, Shutdown Controller
NOTE: This is a summary document.
The complete document is available
under NDA. Please contact an Atmel
Sales Representative.

– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-Time Timer
Reset Controller (RSTC)
– Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control
Shutdown Controller (SHDC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
Clock Generator (CKGR)
– 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent
Slow Clock
– 8 to 16 MHz On-chip Oscillator
– Two PLLs up to 240 MHz
– One USB 480 MHz PLL
Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD)
– 128 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
DMA Controller (DMAC)
– Acts as one Bus Matrix Master
– Embeds 4 Unidirectional Channels with Programmable Priority, Address Generation, Channel
Buffering and Control
– Supports Four External DMA Requests and Four Internal DMA Requests from the Metal
Programmable Block (MPBlock)
Twenty-fourTwenty-two Peripheral DMA Controller Channels (PDC)
One Advanced Encryption System (AES)
– 128/192/256-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications, Protected
Against DPA Attacks
– Buffer Encryption/decryption Capabilities with PDC, including EBC, CBC, OFB, CFB and CTR
Modes of Operation
One Triple Data Encryption System (TDES)
– Compliant with FIPS Publication 46-3, Data Encryption Standard (DES)
– Buffer Encryption/decryption Capabilities with PDC, including EBC, CBC, OFB and CFB
Modes of Operation
2 AT91CAP9SC500A/AT91CAP9SC250A Preliminary

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