CD4025BE Datasheet
Data sheet acquired from Harris Semiconductor SCHS015C – Revised August 2003
The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
Copyright © 2003, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Eco Plan
(1)
Drawing
Qty
(2)
7704403CA CD4001BE CD4001BEE4 CD4001BF CD4001BF3A CD4001BM CD4001BM96 CD4001BM96E4 CD4001BM96G4 CD4001BMT CD4001BNSR CD4001BNSRG4 CD4001BPW CD4001BPWR CD4001BPWRG4 CD4002BE CD4002BF CD4002BF3A CD4002BM
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
CDIP PDIP PDIP CDIP CDIP SOIC SOIC SOIC SOIC SOIC SO SO TSSOP TSSOP TSSOP PDIP CDIP.
CD4000BMS, CD4001BMS CD4002BMS, CD4025BMS
November 1994
CMOS NOR Gate
Pinouts
CD4000BMS TOP VIEW
NC 1 NC 2 A 3 B 4 C 5 H=A+B+C 6 VSS 7 14 VDD 13 F 12 E 11 D 10 K = D + E + F 9 L=G 8 G NC = NO CONNECTION
Features
• High-Voltage Types (20V Rating) • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V • Buffered Inputs and Outputs • Standard Symmetrical Output Characteristics • 100% Tested for Maximum Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requir.
Data sheet acquired from Harris Semiconductor SCHS015C – Revised August 2003
The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
Copyright © 2003, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Eco Plan
(1)
Drawing
Qty
(2)
7704403CA CD4001BE CD4001BEE4 CD4001BF CD4001BF3A CD4001BM CD4001BM96 CD4001BM96E4 CD4001BM96G4 CD4001BMT CD4001BNSR CD4.
Part Number |
CD4025BM |
Manufacturers |
National Semiconductor |
Logo |
|
Description |
Buffered Triple 3-Input NAND/NOR Gate |
Datasheet |
CD4025BM Datasheet (PDF) |
CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate
February 1988
CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate
General Description
These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors They have equal source and sink current capabilities and conform to standard B series output drive The devices also have buffered outputs which improve transfer characteristics by providing very high gain All inputs are protected against static discharge with diodes to VDD and VSS
Features
Y Y Y
Y Y Y
Wide suppl.
Data sheet acquired from Harris Semiconductor SCHS015C – Revised August 2003
The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
Copyright © 2003, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Eco Plan
(1)
Drawing
Qty
(2)
7704403CA CD4001BE CD4001BEE4 CD4001BF CD4001BF3A CD4001BM CD4001BM96 CD4001BM96E4 CD4001BM96G4 CD4001BMT CD4001BNSR CD4.
CMOS NOR Gates
Data sheet acquired from Harris Semiconductor SCHS015C – Revised August 2003
The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
Copyright © 2003, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Eco Plan
(1)
Drawing
Qty
(2)
7704403CA CD4001BE CD4001BEE4 CD4001BF CD4001BF3A CD4001BM CD4001BM96 CD4001BM96E4 CD4001BM96G4 CD4001BMT CD4001BNSR CD4001BNSRG4 CD4001BPW CD4001BPWR CD4001BPWRG4 CD4002BE CD4002BF CD4002BF3A CD4002BM
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
CDIP PDIP PDIP CDIP CDIP SOIC SOIC SOIC SOIC SOIC SO SO TSSOP TSSOP TSSOP PDIP CDIP CDIP SOIC
J
14
1
Non-RoHS
& Green
N
14
25 RoHS & Green
N
14
25 RoHS & Green
J
14
1
Non-RoHS
& Green
J
14
1
Non-RoHS
& Green
D
14
50 RoHS & Green
D
14 2500 RoHS & Green
D
14 2500 RoHS & Green
D
14 2500 RoHS & Green
D
14 250 RoHS & Green
NS 14 2000 RoHS & Green
NS 14 2000 RoHS & Green
PW
14
90 RoHS & Green
PW 14 2000 RoHS & Green
PW 14 2000 RoHS & Green
N
14
25 RoHS & Green
J
14
1
Non-RoHS
& Green
J
14
1
Non-RoHS
& Green
D
14
50 RoHS & Green
.
2021-06-24 : CD4019BF CD4018BM CD4018BF3A CD4018BF CD40174BM CD40175B CD4016BF3A CD4016BE CD4016BF CD40161BE