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CD4027BC

Part Number	CD4027BC
Manufacturer	Fairchild Semiconductor
Description	Dual J-K Master/Slave Flip-Flop
Published	Aug 1, 2014
Detailed Description	CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 Revised January 1999 CD4027BC Dual J-K Master...
Datasheet	CD4027BC PDF File

Overview

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors.
Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs.
These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses.
Set or reset is independent of the clock and is accomplished by a high level on the respective input.
All inputs are protected against damage due...

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