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CDCLVD1216
2:16 Low Additive Jitter LVDS Buffer
Description
CDCLVD1216 www.ti.com SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011 2:16 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1216 FEATURES 1 2:16 Differential Buffer Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz Low Output Skew of 55 ps (Max) Universal Inputs Accept LVDS, LVPECL, LV
CMOS
Selectable Clock Inputs Through Control Pin ...
Texas Instruments
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