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CY7C1265KV18
36-Mbit QDR II+ SRAM Four-Word Burst Architecture
Description
CY7C1263KV18/CY7C1265KV18 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 550 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ...
Cypress Semiconductor
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