(CY7C1355B / CY7C1357B) 9-Mb (256K x 36/512K x 18) Flow-Through SRAM
Description
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CY7C1355B CY7C1357B
9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture
Features
No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock Pin compatible and functionally equivalent ...