36-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Description
CY7C1423KV18/CY7C1424KV18
36-Mbit DDR II SIO SRAM Two-Word Burst Architecture
36-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Features
■ 36-Mbit density (2M × 18, 1M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz ■ Two input clocks ...
