SDRAM. EDD1232AAFA Datasheet

EDD1232AAFA Datasheet PDF

Part EDD1232AAFA
Description 128M bits DDR SDRAM
Feature DATA SHEET 128M bits DDR SDRAM EDD1232AAFA (4M words × 32 bits) Description The EDD1232AAFA is a .
Manufacture Elpida Memory
Datasheet
Download EDD1232AAFA Datasheet

DATA SHEET 128M bits DDR SDRAM EDD1232AAFA (4M words × 32 EDD1232AAFA Datasheet




EDD1232AAFA
DATA SHEET
128M bits DDR SDRAM
EDD1232AAFA (4M words × 32 bits)
Description
The EDD1232AAFA is a 128M bits DDR SDRAM
organized as 1,048,576 words × 32 bits × 4 banks.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in 100-pin plastic LQFP package.
Features
Power supply: VDDQ = 2.5V ± 0.2V
: VDD = 2.5V ± 0.2V
Data rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5, 3
Programmable output driver strength: half/weak
Refresh cycles: 4096 refresh cycles/32ms
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
LQFP package with lead free solder (Sn-Bi)
RoHS compliant
Document No. E0432E50 (Ver.5.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2005



EDD1232AAFA
EDD1232AAFA
Ordering Information
Part number
EDD1232AAFA-6B-E
EDD1232AAFA-7A-E
Mask
version
A
Organization
(words × bits)
4M × 32
Internal
banks
4
Data Rate
Mbps (max.)
333
266
JEDEC speed bin
(CL-tRCDRD-tRP)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
Package
100-pin Plastic
LQFP
Part Number
E D D 12 32 A A FA - 6B - E
Elpida Memory
Type
D: Monolithic Device
Product Family
D: DDR SDRAM
Density / Bank
12: 128M / 4-bank
Organization
32: x32
Power Supply, Interface
A: 2.5V, SSTL_2
Die Rev.
Package
FA: LQFP
Speed
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
Environment Code
E: Lead Free
Data Sheet E0432E50 (Ver.5.0)
2




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