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HEF4015B

NXP
Part Number HEF4015B
Manufacturer NXP
Description Dual 4-bit static shift register
Published Mar 23, 2005
Detailed Description HEF4015B Dual 4-bit static shift register Rev. 9 — 21 March 2016 Product data sheet 1. General description The HEF401...
Datasheet PDF File HEF4015B PDF File

HEF4015B
HEF4015B

Overview
HEF4015B Dual 4-bit static shift register Rev.
9 — 21 March 2016 Product data sheet 1.
General description The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter).
Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (MR).
Information present on D is shifted to the first register position, and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP.
A HIGH on MR clears the register and forces Q0 to Q3 to LOW, independent of CP and D.
The clock input’s Schmitt trigger action makes the input h...


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