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IDCX6

CMOS Gate Array

Description

,'&;[ $0,+* PLFURQ &026 *DWH $UUD\ Description IDCXx is a family of non-inverting, CMOS-level input buffer pieces. Logic Symbol Truth Table IDCXx QC P PADM D PADM QC LL HH HDL Syntax Verilog .................... IDCXx inst_name (QC, PADM); VHDL...................... inst_name: IDCXx port map (QC, PADM); Pin Loading Pin Name PADM (pF) Load IDCX...

AMI

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