M2S28D40ATP-75 PDF File
| Part Number | M2S28D40ATP-75 |
| Manufacturer | Mitsubishi |
| Title | 128M Double Data Rate Synchronous DRAM |
| Description | M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, d... |
| Features |
- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each po... |
| Published | May 2, 2005 |
| Datasheet |
M2S28D40ATP-75 PDF File
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