Part Number | M312L5628BT0-A2 |
Manufacturer | Samsung |
Title | DDR SDRAM Registered Module |
Description | Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0, CK0 CKE0, CKE1(for 2 Row) CS0, CS1(for 2 Row) RAS CAS WE CB0 ~ CB7 Function Address input... |
Features |
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programm... |
Published | May 2, 2005 |
Datasheet | M312L5628BT0-A2 PDF File |