ODCXXX04

2'&;;;[[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description ODCXXXxx is a family of 1 to 24 mA, non-inverting, CMOS-level output buffer pieces. Logic Symbol Truth Table ODCXXXxx A PADM A PADM LL HH HDL Syntax Verilog .................... ODCXXXxx inst_name (PADM, A); VHDL...................... inst_name: ODCXXXxx port map (PADM, A); Pin Loading Pin Name A (eq-load) ODCXXX01 4.3 ODCXXX02 4.3 ODCXXX04 6.2 Load ODCXXX08 8.3 ODCXXX12 8.2 Power Characteristics Cell Output Drive (mA) ODCXXX01 1 ODCXXX02 2 ODCXXX04 4 ODCXXX08 8 ODCXXX12 12 ODCXXX16 16 ODCXXX24 24 a. See page 2-15 for power equation. Power Characteristicsa Static IDD (TJ = 85°C) (nA) TBD EQLpd (Eq-load) 149.5 TBD 155.0 TBD 165.6 TBD 189.8 TBD 210.7 TBD 234.8 TBD 248.2 ODCXXX16 8.2 ODCXXX24 10.3 Pad Logic 4-26 ® Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Capacitive Load (pF) 15 ODCXXX01 From: A tPLH To: PADM tPHL 4.55 4.71 Capacitive ...