Low Skew Buffers
Description
PLL103-11
Low Skew Buffers
FEATURES
Generates 13 copies of High-speed clock inputs. Supports up to three SDRAM DIMMS synchronous clocks. Supports 2-wire I2C serial bus interface with readback. 50% duty cycle with low jitter. Less than 5ns delay. www.DataSheet4U.com Skew between any outputs is less than 250 ps. Tri-state pin for testing. Frequency...
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