| DatasheetsPDF.com |
SN54LS113A FLIP-FLOP Datasheet PDFDUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| Part Number | SN54LS113A |
|---|---|
| Description | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| Feature | SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIG GERED FLIP-FLOP
The SN54 / 74LS113A off ers individual J, K, set, and clock inp uts. These monolithic dual flip-flops a re designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of th e J and K inputs may be allowed to chan ge when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum setup t imes are observed. Input data is transf erred to the outputs on the negative-go ing edge of the clock pulse. DUAL JK N EGATIVE EDGE-TRIGGERED FLIP-FLOP LOW PO WER SCHOTTKY . |
| Manufacture | Motorola Inc |
| Datasheet |
|
|
| Part Number | SN54LS113A |
|---|---|
| Description | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| Feature | SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIG GERED FLIP-FLOP
The SN54 / 74LS113A off ers individual J, K, set, and clock inp uts. These monolithic dual flip-flops a re designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of th e J and K inputs may be allowed to chan ge when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum setup t imes are observed. Input data is transf erred to the outputs on the negative-go ing edge of the clock pulse. DUAL JK N EGATIVE EDGE-TRIGGERED FLIP-FLOP LOW PO WER SCHOTTKY . |
| Manufacture | Motorola Inc |
| Datasheet |
|
|
|
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact) |