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SN54LS175 Datasheet

QUAD D FLIP-FLOP The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A.

Motorola Inc
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Motorola Inc SN54LS175 Datasheet
QUAD D FLIP-FLOP The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. SN54/74LS175 QUAD D FLIP-FLOP LOW POWER SCHOTTKY • • • • • • Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Clock to Output Delays of 30 ns Asynchronous Common Reset True and Complement Output Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 1 MR 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 16 1 D SUFFIX SOIC CASE 751B-03 D0 – D3 CP MR Q0 – Q3 Q0 – Q3 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input True Outputs (Note b) Complemented Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. ORDERING INFORMATION SN54LSX.






SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175, SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDLS068A – DECEMBER 1972 – REVISED OCTOBER 2001 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texa.

Texas Instruments
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Texas Instruments SN54LS175 Datasheet
SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175, SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDLS068A – DECEMBER 1972 – REVISED OCTOBER 2001 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright  2001, Texas Instruments Incorporated 1 SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175, SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDLS068A – DECEMBER 1972 – REVISED OCTOBER 2001 •2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175, SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDLS068A – DECEMBER 1972 – REVISED OCTOBER 2001 •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3 SN54174, SN54175, SN74174, SN74175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDLS068A – DECEMBER 1972 – REVISED OCTOBER 2001 •4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN54LS174, SN54LS175, SN74LS174, SN74LS175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDLS068A – DECEMBER 1972 – REVISED OCTOBER 2001 •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5 SN54S174, SN54S175, SN74S174, SN74S175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDLS068A.






QUAD D FLIP-FLOP

QUAD D FLIP-FLOP The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. SN54/74LS175 QUAD D FLIP-FLOP LOW POWER SCHOTTKY • • • • • • Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Clock to Output Delays of 30 ns Asynchronous Common Reset True and Complement Output Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 1 MR 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 16 1 D SUFFIX SOIC CASE 751B-03 D0 – D3 CP MR Q0 – Q3 Q0 – Q3 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input True Outputs (Note b) Complemented Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. ORDERING INFORMATION SN54LSX.


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