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SN54LS374 Datasheet

Part Number SN54LS374
Manufacturers Texas Instruments
Logo Texas Instruments
Description OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
Datasheet SN54LS374 DatasheetSN54LS374 Datasheet (PDF)

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 D Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package D 3-State Bus-Driving Outputs D Full Parallel Access for Loading D Buffered Control Inputs D Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) D P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S37.

  SN54LS374   SN54LS374






Part Number SN54LS374
Manufacturers Motorola
Logo Motorola
Description OCTAL TRANSPARENT LATCH
Datasheet SN54LS374 DatasheetSN54LS374 Datasheet (PDF)

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN54 /.

  SN54LS374   SN54LS374







OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 D Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package D 3-State Bus-Driving Outputs D Full Parallel Access for Loading D Buffered Control Inputs D Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) D P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374) description These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up. SN54LS373, SN54LS374, SN54S373, SN54S374 . . . J OR W PACKAGE SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE SN74LS374 . . . DB, DW, N, OR NS PACKAGE SN74S373 . . . DW OR N PACKAGE (TOP VIEW) OC 1Q 1D 2D 2Q 3.


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