MEMORY. SN74ABT7820 Datasheet

SN74ABT7820 Datasheet PDF


Part

SN74ABT7820

Description

BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY

Manufacture

etcTI

Page 18 Pages
Datasheet
Download SN74ABT7820 Datasheet


SN74ABT7820 Datasheet
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
D Member of the Texas Instruments
Widebus Family
D Advanced BiCMOS Technology
D Independent Asynchronous Inputs and
Outputs
D Two Separate 512 × 18 FIFOs Buffering
Data in Opposite Directions
D Programmable Almost-Full/Almost-Empty
Flags
D Empty, Full, and Half-Full Flags
D Fast Access Times of 12 ns With a 50-pF
Load and Simultaneous Switching Data
Outputs
D Supports Clock Rates up to 67 MHz
D Package Options Include 80-Pin Quad Flat
(PH) and 80-Pin Thin Quad Flat (PN)
Packages
PH PACKAGE
(TOP VIEW)
RSTA
PENA
AF/AEA
HFA
FULLA
GND
A0
A1
VCC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
VCC
A10
A11
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1 64
2 63
3 62
4 61
5 60
6 59
7 58
8 57
9 56
10 55
11 54
12 53
13 52
14 51
15 50
16 49
17 48
18 47
19 46
20 45
21 44
22 43
23 42
24 41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RSTB
PENB
AF/AEB
HFB
FULLB
GND
B0
B1
VCC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
VCC
B10
B11
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1

SN74ABT7820 Datasheet
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
PN PACKAGE
(TOP VIEW)
AF/AEA
HFA
FULLA
GND
A0
A1
VCC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
VCC
A10
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1 60
2 59
3 58
4 57
5 56
6 55
7 54
8 53
9 52
10 51
11 50
12 49
13 48
14 47
15 46
16 45
17 44
18 43
19 42
20 41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AF/AEB
HFB
FULLB
GND
B0
B1
VCC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
VCC
B10
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT7820 is arranged as two 512 × 18-bit FIFOs for high speed and fast access times. It
processes data at rates up to 67 MHz with access times of 12 ns in a bit-parallel format.
The SN74ABT7820 consists of bus-transceiver circuits, two 512 × 18 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs
(GAB and GBA) control the transceiver functions. The SAB and SBA control inputs select whether real-time or
stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight
fundamental bus-management functions that can be performed with the SN74ABT7820.
The SN74ABT7820 is characterized for operation from 0°C to 70°C.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features Datasheet pdf SN74ABT7820 512 × 18 × 2 STROBED BIDIR ECTIONAL FIRST-IN, FIRST-OUT MEMORY SCA S206D – AUGUST 1991 – REVISED APRIL 1998 D Member of the Texas Instrument s Widebus ™ Family D Advanced BiCMOS Technology D Independent Asynchronous I nputs and Outputs D Two Separate 512 × 18 FIFOs Buffering Data in Opposite Di rections D Programmable Almost-Full/Alm ost-Empty Flags D Empty, Full, and Hal f-Full Flags D Fast Access Times of 12 ns With a 50-pF Load and Simultaneous S witching Data Outputs D Supports Clock Rates up to 67 MHz D Package Options In clude 80-Pin Quad Flat (PH) and 80-Pin Thin Quad Flat (PN) Packages PH PACKAG E (TOP VIEW) GBA SBA GND LDCKA UNCKB E MPTYB VCC VCC VCC VCC EMPTYA UNCKA LDCK B GND SAB GAB RSTA PENA AF/AEA HFA FUL LA GND A0 A1 VCC A2 A3 GND A4 A5 GND A6 A7 GND A8 A9 VCC A10 A11 GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 5 7 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 26 27 28 29.
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