PREAMPLIFIER. TDA9206 Datasheet

TDA9206 Datasheet PDF


Part TDA9206
Description I2C BUS CONTROLLED 130MHz RGB PREAMPLIFIER
Feature TDA9206 I2C BUS CONTROLLED 130MHz RGB PREAMPLIFIER . . . . . . . . . . 130MHz TYPICAL BANDWIDTH AT.
Manufacture ST Microelectronics
Datasheet
Download TDA9206 Datasheet


TDA9206 I2C BUS CONTROLLED 130MHz RGB PREAMPLIFIER . . . . TDA9206 Datasheet




TDA9206
TDA9206
I2C BUS CONTROLLED 130MHz RGB PREAMPLIFIER
. 130MHz TYPICAL BANDWIDTH AT 2VPP
OUTPUT WITH 12pF CAPACITIVE LOAD
. 2.8ns TYPICAL RISE/FALL TIME AT 2VPP
OUTPUT WITH 12pF CAPACITIVE LOAD
. POWERFULL OUTPUT DRIVE CAPABILITY
. BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSE WIDTH ARE I2C BUS CONTROLLED
. INTERNAL BACK-PORCH CLAMPING
PULSE GENERATOR
. OSD WHITE BALANCE TRACKING
. INTERNAL OSD SWITCHES
. BLANKING AND FAST-BLANKING INPUTS
. VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB)
. SEMI-TRANSPARENT BACKGROUND ON
OSD PICTURE
DIP24
(Plastic Package)
ORDER CODE : TDA9206
PIN CONNECTIONS
DESCRIPTION
The TDA9206 is a digitaly controlled wideband
video preamplifier intended for use in high resolu-
tion color monitor. All controls and adjustments are
digitaly performed thanks to I2C serial bus. Con-
trast, brightness and DC output level of RGB sig-
nals are common to the 3 channels and drive
adjustment is separate for each channel. Three I2C
gain controlled OSD inputs can be switched with
RGB signals using fast blanking command. Clamp-
ing of RGB signals is performed thanks to a flexible
integrated system. The white balance adjustment
is effective on brightness, video and OSD signals.
The TDA9206works for application usingAC or DC
coupled CRT driver.
Because of its features and due to component
saving the TDA9206 leads to a very performantand
cost effective application.
September 1996
IN1
OSD1
AVDD
IN2
OSD2
AGND
IN3
OSD3
LVDD
LGND
SDA
SCL
1
2
3
4
5
6
7
8
9
10
11
12
24 HSYNC
23 PVCC1
22 OUT1
21 PGND1
20 PVCC2
19 OUT2
18 PGND2
17 PVCC3
16 OUT3
15 PGND3
14 BLK
13 FBLK
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TDA9206
TDA9206
PIN DESCRIPTION
Name
IN1
OSD1
AVDD
IN2
OSD2
AGND
IN3
OSD3
LVDD
LGND
SDA
SCL
Pin Type
Function
1 I 1st Channel Main Picture Input
2 I 1st Channel OSD Input
3 I 12V Analog VDD
4 I 2nd Channel Main Picture Input
5 I 2nd Channel OSD Input
6 I/O Analog Ground
7 I 3rd Channel Main Picture Input
8 I 3rd Channel OSD Input
9 I 12V Logic VDD
10 I/O Logic Ground
11 I/O Serial Data Line
12 I Serial Clock Line
Name Pin Type
Function
FBLK 13 I Fast Blanking Input
BLK
PGND3
OUT3
PVCC3
PGND2
OUT2
PVCC2
PGND1
OUT1
PVCC1
14
15
16
17
18
19
20
21
22
23
I Blanking Input
I/O 3rd Channel Power Ground
O 3rd Channel Output
I 3rd Channel Power VCC
I/O 2nd Channel Power Ground
O 2nd Channel Output
I 2nd Channel Power VCC
I/O 1st Channel Power Ground
O 1st Channel Output
I 1st Channel Power VCC
HSYNC 24 I Horizontal Synch Input
BLOCK DIAGRAM
BLK
14
FBLK
13
C LAMP
AVDD 3
VREF
CO NTRAST
IN1 1
AGND 6
IN2 4
BLUE CHANNEL
IN3 7
GREEN C HANNEL
LVDD 9
LGND 10
BP CP
LATCHES
I2C
BUS D/A
DE C O DE R
OSD
C O NT
TDA92 0 6
24
HS YNC
11 12
SDA SCL
2
O S D1
P VCC1
23
BR IGHTNE S S
DR IVE
BP C P
O UTP UT
S TAG E
8 bits
22 OUT1
21 PGND1
20 P VCC2
19 OUT2
18 PGND2
16 OUT3
17 P VCC3
15 PGND3
5
O S D2
I2C
8
O S D3
VREF
O UTPUT
DC LEVEL
ADJ US T
2/12






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