Msps. TDC1044AR4C Datasheet
Monolithic Video A/D Converter
4-Bit, 25 Msps
• 4-bit resolution
• 1/4 LSB non-linearity
• Sample-and-hold circuit not required
• 25 Msps conversion rate
• Selectable output format
• 16-lead DIP and 20-lead PLCC packages
• Digital communications
• Video special effects
• Radar data conversion
• Medical imaging
The TDC1044A is a 25 Msps (Megasample per second) full-
parallel analog-to-digital converter, capable of converting an
analog signal with full-power frequency components up to
12.5 MHz into 4-bit digital words. Use of a sample-and-hold
circuit is not necessary for operation of the TDC1044A. All
digital inputs and outputs are TTL compatible.
The TDC1044A consists of 15 latching comparators, encod-
ing logic, and an output register. A single convert signal
controls the conversion operation. Output formats are
true/inverted binary or true/inverted offset two’s complement
15 TO 4
The TDC1044A has three functional sections: a comparator
array, encoding logic, and an output register. The comparator
array compares the input signal with 15 reference voltages to
produce an N-of-15 thermometer code. All the comparators
referred to voltages more positive than the input signal will
be off, and those referred to voltages more negative than the
input signal will be on. Encoding logic converts the N-of-15
code into binary or two’s complement coding and can invert
either output code. This coding function is controlled by DC
signals on pins NMINV and NLINV. The output register
holds the output constant between updates.
The TDC1044A operates from two power supply voltages,
+5.0V and -5.2V. The return for ICC (the current drawn from
the +5.0V supply) is DGND. The return for IEE (the current
drawn from the -5.2V supply) is AGND. All power and
ground pins must be connected.
The TDC1044A converts analog signals in the range
VRB £ VIN £ VRB into digital form. VRB (the voltage
applied to RB at the bottom of the reference resistor chain)
and VRT (the voltage applied to RB at the top of the refer-
ence resistor chain) should be between +0.1V and -1.1V.
VRT should be more positive than VRB within that range.
The voltage applied across the reference resistor chain
(VRT – VRB) must be between 0.4V and 1.3V.
Nominal voltages are VRT = 0.00V and VRB = -1.00V. These
voltages may be varied dynamically up to 10MHz. Due to
slight variation in the reference currents with clock and input
signals, RT and RB should be low-impedance points. For cir-
cuits in which the reference is not varied, a bypass capacitor
to ground is recommended. If the reference inputs are varied
dynamically (as in an Automatic Gain Control circuit), a
low-impedance reference source is required.
A reference middle, RM, is also provided; this may be used
as an input to adjust the mid-scale point in order to improve
integral linearity. This point may also be used as a tap to sup-
ply a mid-scale voltage to offset the analog input. If VRM is
used as an output, it must be connected to a high input
impedance device which has small input current. Noise at
this point may adversely affect the performance of this
Two function control pins, NMINV and NLINV, set the out-
put format to be either straight binary or offset two’s comple-
ment, in either true or inverted sense, according to Table 1.
These pins are active LOW as signiﬁed by the preﬁx "N" in
the signal name. They may be tied to VCC for a logic "1" and
DGND for a logic "0."
NMINV controls the MSB, D1; NLINV controls the three
LSBs: D2, D3 and D4.
The TDC1044A requires a CONVert (CONV) signal. A sam-
ple is taken (the comparators are latched) within tSTO after a
rising edge of CONV. The coded result is translated to the
output latches on the next rising edge. The outputs hold the
previous data a minimum time (tHO) after the rising edge of
the CONV signal. New data becomes valid after a maximum
delay time, tD.
The TDC1044A uses latching comparators which cause the
input impedance to vary slightly with the signal level. For
optimal performance, the source impedance of the driving
circuit must less than 25 Ohms. Within the range of VEE to
+0.5V, the input signal will not damage the device. If the
input signal is at a voltage between VRT and VRB, the output
will be a binary code between 0 and 15 inclusive. A signal
outside this range will indicate either full-scale positive or
full-scale negative, depending on whether the signal is off-
scale in the positive or negative direction.
TDC1044A outputs are TTL compatible, and capable of
driving four low-power Schottky TTL (54/74 LS) unit loads.
The outputs hold the previous data a minimum time (tHO)
after the rising edge of the CONV signal. Data becomes
valid after a maximum delay time (tD) after the rising edge
of CONV. For optimum performance, 2.2 kOhm pull-up
resistors are recommended.
Pin 3 of the TDC1044A is labeled No Connect (NC), and has
no connection to the chip. Connect this pin to AGND for best
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