PROMs. TDOXZ Datasheet

TDOXZ Datasheet PDF


Part TDOXZ
Description XC1800 Series of In-System Programmable Configuration PROMs
Feature d 0 ® XC1800 Series of In-System Programmable Configuration PROMs 0 6* September 17, 1999 (Versi.
Manufacture Xilinx Inc
Datasheet
Download TDOXZ Datasheet


d 0 ® XC1800 Series of In-System Programmable Configurati TDOXZ Datasheet




TDOXZ
d
®
September 17, 1999 (Version 1.3)
0
XC1800 Series of In-System
Programmable Configuration
PROMs
0 6* Preliminary Product Specification
Features
• In-system programmable 3.3V PROMs for configuration
of Xilinx FPGAs
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• IEEE Std 1149.1 boundary-scan (JTAG) support
• Simple interface to the FPGA; could be configured to
use only one user I/O pin
• Cascadable for storing longer or multiple bitstreams
• Dual configuration modes
- Serial Slow/Fast configuration (up to 15 mHz).
- Parallel
• Low-power advanced CMOS FLASH process
• 5 V tolerant I/O pins accept 5 V, 3.3 V and 2.5 V signals.
• 3.3 V or 2.5 V output capability
• Available in PC20, SO20, PC44 and VQ44 packages.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• JTAG command initiation of standard FPGA
configuration.
Description
Xilinx introduces the XC1800 series of in-system program-
mable configuration PROMs. Initial devices in this 3.3V
family are a 4 megabit, a 2 megabit, a 1 megabit, a 512
Kbit, a 256 Kbit, and a 128 Kbit PROM that provide an
easy-to-use, cost-effective method for re-programming and
storing large Xilinx FPGA or CPLD configuration bit-
streams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising CCLK, data is available on the PROM
DATA (D0) pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA are clocked by an
external clock.
When the FPGA is in Express or SelectMAP Mode, an
external oscillator will generate the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, data are available on the PROM’s DATA (D0-D7)
pins. The data will be clocked into the FPGA on the follow-
ing rising edge of the CCLK. Neither Express nor Select-
MAP utilize a Length Count, so a free-running oscillator
may be used. See Figure 5
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC1700L one-time programmable Serial PROM family.
CLK CE
OE/Reset
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Address
Memory
Data
Serial
or
Parallel
Interface
CF
Figure 1: XC1800 Series Block Diagram
September 17, 1999 (Version 1.3)
CEO
D0 DATA
(Serial or Parallel
(Express/SelectMAP) Mode)
D1 - D7
Express Mode and
SelectMAP Interface
99020300
1



TDOXZ
XC1800 Series of In-System Programmable Configuration PROMs
Pinout and Pin Description
Table 1: Pin Names and Descriptions
Pin
Name
Boundary
Scan
Order
Function
Pin Description
D0 4 DATA OUT D0 is the DATA output pin to provide data
3 OUTPUT for configuring an FPGA in serial mode.
ENABLE
D1 6 DATA OUT D0- D7 are the output pins to provide par-
5
OUTPUT
ENABLE
allel data for configuring a Xilinx FPGA in
express mode.
D2 2 DATA OUT
1 OUTPUT
ENABLE
D3 8 DATA OUT
7 OUTPUT
ENABLE
D4 24 DATA OUT
23 OUTPUT
ENABLE
D5 10 DATA OUT
9 OUTPUT
ENABLE
D6 17 DATA OUT
16 OUTPUT
ENABLE
D7 14 DATA OUT
13 OUTPUT
ENABLE
CLK 0
DATA IN
Each rising edge on the CLK input incre-
ments the internal address counter if both
CE is low and OE/RESET is high.
OE/
RESET
20
19
18
DATA IN When Low, this input holds the address
DATA OUT
counter reset and the DATA output at
high impedance.
OUTPUT
ENABLE
CE 15 DATA IN When CE is High, this pin puts the device
into standby mode. The DATA output pin
is at High impedance, and the device is in
low power standby mode.
CF 22 DATA OUT Allows JTAG CONFIG instruction to ini-
21
DATA IN
tiate FPGA configuration without power-
ing down FPGA.
44-pin
VQFP
40
29
42
27
9
25
14
19
43
13
15
10
R
44-pin
PLCC
2
20-pin
SOIC & PLCC
1
35 16
42
33 15
15 7*
31 14
20 9
25 12
53
19 8
21 10
16 7*
2 September 17, 1999 (Version 1.3)






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