MODULES. TM4EP72DPN Datasheet

TM4EP72DPN Datasheet PDF


Part

TM4EP72DPN

Description

EXTENDED-DATA-OUT DYNAMIC RAM MODULES

Manufacture

etcTI

Page 30 Pages
Datasheet
Download TM4EP72DPN Datasheet


TM4EP72DPN Datasheet
TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN
TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN
EXTENDEDĆDATAĆOUT DYNAMIC RAM MODULES
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
D Organization
− TM2EP64DxN . . . 2 097 152 × 64 Bits
− TM2EP72DxN . . . 2 097 152 × 72 Bits
− TM4EP64DxN . . . 4 194 304 × 64 Bits
− TM4EP72DxN . . . 4 194 304 × 72 Bits
D Single 3.3-V Power Supply
(±10% Tolerance)
D TM2EP64DxN — Uses Eight 16M-Bit
(2M × 8-Bit) Dynamic Random Access
Memories (DRAMs) in Thin Small-Outline
Package (TSOP), or Small-Outline J-Lead
Package (SOJ)
D TM2EP72DxN — Uses Nine 16M-Bit
(2M × 8-Bit) DRAMs in TSOP, or SOJ
D TM4EP64DxN — Uses 16 16M-Bit
(2M × 8-Bit) DRAMs in TSOP, or SOJ
D TM4EP72DxN — Uses 18 16M-Bit
(2M × 8-Bit) DRAMs in TSOP, or SOJ
D Performance ranges
ACCESS ACCESS ACCESS
TIME TIME TIME
tRAC tCAC tAA
MAX MAX MAX
EDO
CYCLE
tHPC
MIN
’xEPxxDxN-50
’xEPxxDxN-60
’xEPxxDxN-70
50 ns
60 ns
70 ns
13 ns
15 ns
18 ns
25 ns
30 ns
35 ns
20 ns
25 ns
30 ns
D JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) Without Buffer for Use With
Socket
D High-Speed, Low-Noise LVTTL Interface
D Long Refresh Period: 32 ms (2 048 Cycles)
D 3-State Output
D Extended-Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
D Serial Presence Detect (SPD) Using
EEPROM
D Ambient Air Temperature Range
0°C to 70°C
D Gold-Plated Contacts
description
The TM2EP64DPN is a 16M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of
eight TMS427809A, 2 097 152 byte × 8-bit 2K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature
number SMKS887). The TM2EP64DJN is available with an SOJ package (DZ suffix).
The TM2EP72DPN is a 16M-byte, 168-pin DIMM. The DIMM is composed of nine TMS427809A,
2 097 152 byte × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the
TMS427809A data sheet (literature number SMKS887). The TM2EP72DJN is available with an SOJ package
(DZ suffix).
The TM4EP64DPN is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of
sixteen TMS427809A, 2 097 152 × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling
capacitors. The TM4EP64DJN is available with an SOJ package (DZ suffix).
The TM4EP72DPN is a 32M-byte, 168-pin DIMM. The DIMM is composed of 18 TMS427809A, 2097152 × 8-bit
2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet
(literature number SMKS887). The TM4EP72DJN is available with an SOJ package (DZ suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1

TM4EP72DPN Datasheet
TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN
TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN
EXTENDEDĆDATAĆOUT DYNAMIC RAM MODULES
SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998
operation
The TMxEPxxDxN DIMMs operate as displayed in Table 1.
DIMM
TM2EP64DxN
TM2EP72DxN
TM4EP64DxN
TM4EP72DxN
Table 1. TMxEPxxDxN DIMM Device Table
DEVICE AND QUANTITY ( )
TMS427809A (8)
TMS427809A (9)
TMS427809A (16)
TMS427809A (18)
Connected as shown in the functional
block diagram.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443


Features Datasheet pdf TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4E P64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72D PN, TM4EP72DJN EXTENDEDĆDATAĆOUT DYNA MIC RAM MODULES SMMS684A − AUGUST 199 7 − REVISED FEBRUARY 1998 D Organiza tion − TM2EP64DxN . . . 2 097 152 × 64 Bits − TM2EP72DxN . . . 2 097 152 × 72 Bits − TM4EP64DxN . . . 4 194 3 04 × 64 Bits − TM4EP72DxN . . . 4 19 4 304 × 72 Bits D Single 3.3-V Power Supply (±10% Tolerance) D TM2EP64DxN — Uses Eight 16M-Bit (2M × 8-Bit) Dy namic Random Access Memories (DRAMs) i n Thin Small-Outline Package (TSOP), o r Small-Outline J-Lead Package (SOJ) D TM2EP72DxN — Uses Nine 16M-Bit (2M × 8-Bit) DRAMs in TSOP, or SOJ D TM4E P64DxN — Uses 16 16M-Bit (2M × 8-Bit ) DRAMs in TSOP, or SOJ D TM4EP72DxN Uses 18 16M-Bit (2M × 8-Bit) DRAMs in TSOP, or SOJ D Performance ranges ACCESS ACCESS ACCESS TIME TIME TIME tRA C tCAC tAA MAX MAX MAX EDO CYCLE tHPC MIN ’xEPxxDxN-50 ’xEPxxDxN-60 ’x EPxxDxN-70 50 ns 60 ns 70 ns 13 ns 15 ns 18 ns 25 ns 30 ns 35 ns 20 ns 25 ns 30 ns D JEDEC 168-.
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