DSP FPGA. XC3SD1800A Datasheet

XC3SD1800A Datasheet PDF

Part Number



Spartan-3A DSP FPGA



Total Page 30 Pages
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Spartan-3A DSP FPGA Family Data Sheet
DS610 October 4, 2010
Module 1:
Introduction and Ordering Information
DS610 (v3.0) October 4, 2010
• Introduction
• Features
• Architectural Overview
• Configuration Overview
• General I/O Capabilities
• Supported Packages and Package Marking
• Ordering Information
Module 2:
Functional Description
DS610 (v3.0) October 4, 2010
The functionality of the Spartan®-3A DSP FPGA family is
described in the following documents.
UG331: Spartan-3 Generation FPGA User Guide
• Clocking Resources
• Digital Clock Managers (DCMs)
• Block RAM
• Configurable Logic Blocks (CLBs)
- Distributed RAM
- SRL16 Shift Registers
- Carry and Arithmetic Logic
• I/O Resources
• Programmable Interconnect
• ISE® Software Design Tools and IP Cores
• Embedded Processing and Control Solutions
• Pin Types and Package Overview
• Package Drawings
• Powering FPGAs
• Power Management
UG332: Spartan-3 Generation Configuration User Guide
• Configuration Overview
• Configuration Pins and Behavior
• Bitstream Sizes
• Detailed Descriptions by Mode
- Master Serial Mode using Platform Flash PROM
- Master SPI Mode using Commodity Serial Flash
- Master BPI Mode using Commodity Parallel Flash
- Slave Parallel (SelectMAP) using a Processor
- Slave Serial using a Processor
- JTAG Mode
• ISE iMPACT Programming Examples
• MultiBoot Reconfiguration
• Design Authentication using Device DNA
Product Specification
UG431: XtremeDSP™ DSP48A for Spartan-3A DSP
FPGAs User Guide
• DSP48A Slice Design Considerations
• DSP48A Architecture Highlights
- 18 x 18-Bit Multipliers
- 48-Bit Accumulator
- 18-bit Pre-Adder
• DSP48A Application Examples
Module 3:
DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
• DC Electrical Characteristics
• Absolute Maximum Ratings
• Supply Voltage Specifications
• Recommended Operating Conditions
• Switching Characteristics
• I/O Timing
• Configurable Logic Block (CLB) Timing
• Digital Clock Manager (DCM) Timing
• Block RAM Timing
• XtremeDSP Slice Timing
• Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS610 (v3.0) October 4, 2010
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS610 October 4, 2010
Product Specification

DS610 (v3.0) October 4, 2010
Spartan-3A DSP FPGA Family:
Introduction and Ordering Information
Product Specification
The Spartan®-3A DSP family of Field-Programmable Gate Arrays
(FPGAs) solves the design challenges in most high- volume,
cost-sensitive, high-performance DSP applications. The
two-member family offers densities ranging from 1.8 to 3.4 million
system gates, as shown in Table 1.
The Spartan-3A DSP family builds on the success of the
Spartan-3A FPGA family by increasing the amount of memory per
logic and adding XtremeDSP™ DSP48A slices. New features
improve system performance and reduce the cost of configuration.
These Spartan-3A DSP FPGA enhancements, combined with
proven 90 nm process technology, deliver more functionality and
bandwidth per dollar than ever before, setting the new standard in
the programmable logic and DSP processing industry.
The Spartan-3A DSP FPGAs extend and enhance the Spartan-3A
FPGA family. The XC3SD1800A and the XC3SD3400A devices
are tailored for DSP applications and have additional block RAM
and XtremeDSP DSP48A slices. The XtremeDSP DSP48A slices
replace the 18x18 multipliers found in the Spartan-3A devices and
are based on the DSP48 blocks found in the Virtex®-4 devices.
The block RAMs are also enhanced to run faster by adding an
output register. Both the block RAM and DSP48A slices in the
Spartan-3A DSP devices run at 250 MHz in the lowest cost,
standard -4 speed grade.
Because of their exceptional DSP price/performance ratio,
Spartan-3A DSP FPGAs are ideally suited to a wide range of
consumer electronics applications, such as broadband access,
home networking, display/projection, and digital television.
The Spartan-3A DSP family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, lengthy
development cycles, and the inherent inflexibility of conventional
ASICs. Also, FPGA programmability permits design upgrades in
the field with no hardware replacement necessary, an impossibility
with ASICs.
• Very low cost, high-performance DSP solution for
high-volume, cost-conscious applications
• 250 MHz XtremeDSP DSP48A Slices
• Dedicated 18-bit by 18-bit multiplier
• Available pipeline stages for enhanced performance of at
least 250 MHz in the standard -4 speed grade
• 48-bit accumulator for multiply-accumulate (MAC) operation
• Integrated adder for complex multiply or multiply-add
• Integrated 18-bit pre-adder
• Optional cascaded Multiply or MAC
• Hierarchical SelectRAM™ memory architecture
• Up to 2268 Kbits of fast block RAM with byte write enables
for processor applications
• Up to 373 Kbits of efficient distributed RAM
• Registered outputs on the block RAM with operation of at
least 280 MHz in the standard -4 speed grade
• Dual-range VCCAUX supply simplifies 3.3V-only design
• Suspend, Hibernate modes reduce system power
• Low-power option reduces quiescent current
• Multi-voltage, multi-standard SelectIO™ interface pins
• Up to 519 I/O pins or 227 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• Selectable output drive, up to 24 mA per pin
• QUIETIO standard reduces I/O switching noise
• Full 3.3V ± 10% compatibility and hot swap compliance
• 622+ Mb/s data transfer rate per differential I/O
• LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with
integrated differential termination resistors
• Enhanced Double Data Rate (DDR) support
• DDR/DDR2 SDRAM support up to 333 Mb/s
• Fully compliant 32-/64-bit, 33/66 MHz PCI support
• Abundant, flexible logic resources
• Densities up to 53712 logic cells, including optional shift
• Efficient wide multiplexers, wide logic, fast carry logic
• IEEE 1149.1/1532 JTAG programming/debug port
• Eight Digital Clock Managers (DCMs)
• Clock skew elimination (delay locked loop)
• Frequency synthesis, multiplication, division
• High-resolution phase shifting
• Wide frequency range (5 MHz to over 320 MHz)
• Eight low-skew global clock networks, eight additional clocks
per half device, plus abundant low-skew routing
• Configuration interface to industry-standard PROMs
• Low-cost, space-saving SPI serial Flash PROM
• x8 or x8/x16 BPI parallel NOR Flash PROM
• Low-cost Xilinx® Platform Flash with JTAG
• Unique Device DNA identifier for design authentication
• Load multiple bitstreams under FPGA control
• Post-configuration CRC checking
MicroBlaze™ and PicoBlazeembedded processor cores
• BGA and CSP packaging with Pb-free options
• Common footprints support easy density migration
XA Automotive version available
Table 1: Summary of Spartan-3A DSP FPGA Attributes
CLB Array (One CLB = Four Slices)
System Equivalent
Total Total
Gates Logic Cells Rows Columns CLBs Slices
1800K 37,440
48 4,160 16,640
3400K 53,712 104 58 5,968 23,872
1. By convention, one Kb is equivalent to 1,024 bits.
User I/O
I/O Pairs
© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS610 (v3.0) October 4, 2010
Product Specification

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