• Two Independent APLL Channels
• Four Input Clocks Per Channel
• One crystal/CMOS input
• Two differential/CMOS inputs
• One single-ended/CMOS input
• Any input frequency from 9.72MHz to 1250MHz (9.72MHz to 300MHz for CMOS)
• Clock selection by pin or register control
• Low-Jitter Fractional-N APLL...
ZL30244 PDF File
