EFFECT TRANSISTOR. NP55N04SLG Datasheet

NP55N04SLG TRANSISTOR. Datasheet pdf. Equivalent

Part NP55N04SLG
Description MOS FIELD EFFECT TRANSISTOR
Feature NP55N04SLG MOS FIELD EFFECT TRANSISTOR Preliminary Data Sheet R07DS0242EJ0100 Rev.1.00 Feb 23, 2011.
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NP55N04SLG MOS FIELD EFFECT TRANSISTOR Preliminary Data She NP55N04SLG Datasheet
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NP55N04SLG
NP55N04SLG
MOS FIELD EFFECT TRANSISTOR
Preliminary Data Sheet
R07DS0242EJ0100
Rev.1.00
Feb 23, 2011
Description
The NP55N04SLG is N-channel MOS Field Effect Transistor designed for high current switching applications.
Features
Channel temperature 175 degree rating
Super low on-state resistance
RDS(on)1 = 6.5 mΩ MAX. (VGS = 10 V, ID = 28 A)
RDS(on)2 = 8.5 mΩ MAX. (VGS = 5 V, ID = 28 A)
RDS(on)3 = 15 mΩ MAX. (VGS = 4.5 V, ID = 11 A)
Low input capacitance
Gate to Source ESD protection diode built-in
Ordering Information
Part No.
LEAD PLATING
PACKING
NP55N04SLG-E1-AY 1
NP55N04SLG-E2-AY 1
Pure Sn (Tin)
Tape 2500 p/reel
Note: 1. Pb-free (This product does not contain Pb in external electrode.)
Package
TO-252 (MP-3ZK)
Absolute Maximum Ratings (TA = 25°C)
Item
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) 1
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
Storage Temperature
Repetitive Avalanche Current 2
Repetitive Avalanche Energy 2
Symbol
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
PT2
Tch
Tstg
IAR
EAR
Ratings
40
±20
±55
±220
77
1.2
175
55 to +175
30
90
Unit
V
V
A
A
W
W
°C
°C
A
mJ
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance ∗2
Rth(ch-C)
Rth(ch-A)
1.95 °C/W
125 °C/W
Notes: 1. PW 10 μs, Duty Cycle 1%
2. Starting Tch 150°C, VDD = 20 V, RG = 25 Ω, VGS = 20 0 V
R07DS0242EJ0100 Rev.1.00
Feb 23, 2011
Page 1 of 6



NP55N04SLG
NP55N04SLG
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold
Voltage
Forward Transfer Admittance 1
Drain to Source On-state
Resistance 1
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage 1
Reverse Recovery Time
Reverse Recovery Charge
Note: 1. Pulsed test
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)1
RDS(on)2
RDS(on)3
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
Min
1.5
12
Typ
2.0
32
4.7
5.7
6.3
2700
310
200
15
17
60
8
57
9
17
0.9
30
28
Max
1
±10
2.5
6.5
8.5
15
4050
465
380
33
43
120
20
86
1.5
Chapter Title
Unit
μA
μA
V
S
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 10 V, ID = 28 A
VGS = 10 V, ID = 28 A
VGS = 5.0 V, ID = 28 A
VGS = 4.5 V, ID = 11 A
VDS = 25 V,
VGS = 0 V,
f = 1 MHz
VDD = 20 V, ID = 28 A,
VGS = 10 V,
RG = 0 Ω
VDD = 32 V,
VGS = 10 V,
ID = 55 A
IF = 55 A, VGS = 0 V
IF = 55 A, VGS = 0 V,
di/dt = 100 A/μs
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off) tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
R07DS0242EJ0100 Rev.1.00
Feb 23, 2011
Page 2 of 6





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