CS22210 CONTROLLER. Datasheet pdf. Equivalent

Part CS22210
Feature CS22210 Data Sheet Wireless PCI/USB Controller 1 Description The Cirrus Logic CS22210 Wireless Netw.
Manufacture Cirrus Logic
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CS22210 Data Sheet Wireless PCI/USB Controller 1 Descriptio CS22210 Datasheet
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CS22210 Data Sheet
Wireless PCI/USB Controller
1 Description
The Cirrus Logic CS22210 Wireless Network Controller enables high speed, 11 Mbps digital wireless
data connectivity for wireless data connectivity for PCI, mobile, embedded systems and other cost
sensitive applications.
The CS22210 is a highly integrated single-chip PCI / USB solution for wireless networks supporting video,
audio, voice, and data traffic. The programmable controller executes Cirrus Logic’s Whitecap™2
networking protocol that provides Wi-Fi™ (802.11b) compliance as well as multimedia and quality of
service (QoS) support. The device includes several high performance components including an
ARM7TDMI RISC processor core, a Forward Error Correction (FEC) codec and a wireless Radio MAC
supporting up to11 Mbps throughput. The CS22210 is designed to support both a standard PCI 2.1 or
PCI 2.2 compliant interface or USB 1.1 compliant device interface making it an ideal choice for cost
effective standalone and embedded high-speed wireless networking products.
The CS22210 utilizes state-of-the-art 0.18um CMOS process and is housed in a 208 MQFP package
designed to provide integrated low cost IEEE 802.11 standard compliant system solutions. The core is
powered at 1.8 V to reduce overall power consumption. In addition, the CS22210 supports various power
management modes for host, MAC, baseband, and radio interfaces.
Figure 1. Example System Block Diagram
PCI or USB Host
802.11b compatible
2.4 GHz
Digital Radio
PHY Transceiver
11 Mbps
Baseband I/F
Networking Data
2.4 GHz Direct Sequence
Spread Spectrum
System Memory
SDRAM (Up to 4MB)
SRAM (Up to 256KB)
Boot ROM/Flash
(Up to 1MB)
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2 Features
Embedded ARM Core and System Support Logic
High performance ARM7TDMI RISC processor core at 77MHz
4KB integrated, one-way set associative, unified, write through cache
Individual interrupt for each functional block
Two 23-bit programmable (periodic or one-shot) general purpose timers
8 Dword (32-bits) memory write and read buffers for high system performance
Abort cycle detection and reporting for debugging
ARM performance monitoring function for system fine-tuning
Programmable performance improvement logic based on system configuration
Flexible independent DMA engines for PCI, USB and digital radio functional units
Enhanced Memory Controller Unit
Programmable memory controller unit supporting SDRAM /async SRAM/boot ROM interface
16-bit data bus with 12-bit address supporting up to 4MB at up to 103MHz SDRAM
8-bit data bus with addressing support up to 1MB of boot ROM/Flash
Programmable SDRAM timing and size parameters such as CAS latencies and number of banks
columns and rows
FEC codec
High performance Reed-Solomon coding for error correction (255:239 block coding)
Reduces symbol error probability of a typical 10e-3 error rate environment to 10e-9
Programmable rate FEC engine to optimize channel efficiency
Low latency, fully pipelined hardware encoding and decoding. Support byte wise single cycle throughput
up to 77MHz, with a sustain rate of 77MBps.
Double buffering (64 Dword read/write buffer) to enhance system performance
On the fly configuration of encoder and decoder
Digital Wireless Radio MAC
Standard interface to 802.11b radio baseband transceiver
11Mbps data rate
32 Dword transmit/receive FIFO
Supports clear channel assessment (CCA)
Power Management
Host (PCI or USB) ACPI compliant
Remote USB host wakeup
Supports variable rate radio transmit, receive and standby radio power modes through two DACs
Clock and PLL Interface
Single 44MHz crystal oscillator reference clock for PCI version; 48MHz reference clock required in USB
Internal PLL to generate internal and on board clocks
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