Schmitt Trigger. CHT-74132 Datasheet

CHT-74132 Trigger. Datasheet pdf. Equivalent


Part CHT-74132
Description Quad 2-Input NAND Schmitt Trigger
Feature The Leader in High Temperature Semiconductor Solutions CHT-74132 DATASHEET Version: 3.7 8-Jul-14 (.
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CHT-74132
The Leader in High Temperature
Semiconductor Solutions
CHT-74132 DATASHEET
Version: 3.7
8-Jul-14
(Last Modification Date)
High-Temperature, Quad 2-Input NAND Schmitt
Trigger
General Description
The CHT-74132 contains four independent
2-input NAND gates with Schmitt Trigger,
performing the Boolean function :
Y AB
The gate switches at different points for
positive and negative going signals. The
difference between the positive voltage VT+
and the negative voltage VT- is defined as
the hysteresis voltage VH
The CHT-74132 can operate with supply
voltages from 3.3 to 5V (±10%).
Features
Qualified from -55 to +225°C (Tj)
3.3 to 5V (±10%) supply voltages
Latchup-free at any supply and tem-
perature condition
Validated at 225°C for 30000 hours
(CDIL14) and 20000 hours (CSOIC16)
(and still on-going)
Available in CDIL14 and CSOIC 16
hermetic standard package
Applications
High temperature logic
Noise immunity function
Sensor interface
Signal processing/conditioning
Package and Pin Configuration
IN1 A 1
DIL14
14 VDD
IN1 B 2
13 IN4 A
OUT1 3
12 IN4 B
IN2 A 4
11 OUT4
IN2 B 5
10 IN3 A
OUT2 6
9 IN3 B
VSS 7
8 OUT3
Pin Symbol Description
1 IN1 A Input A of the NAND gate number 1
2 IN1 B Input B of the NAND gate number 1
3 OUT1 Output of the NAND gate number 1
4 IN2 A Input A of the NAND gate number 2
5 IN2 B Input B of the NAND gate number 2
6 OUT2 Output of the NAND gate number 2
7 VSS Circuit core ground terminal.
8 OUT3 Output of the NAND gate number 3
9 IN3 B Input B of the NAND gate number 3
10 IN3 A Input A of the NAND gate number 3
11 OUT4 Output of the NAND gate number 4
12 IN4 B Input B of the NAND gate number 4
13 IN4 A Input A of the NAND gate number 4
14 VDD
Circuit core power supply terminal.
PUBLIC
Doc. DS-080294 V3.7
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CHT-74132
8-Jul-14
(Last Modification Date)
IN1 A 1
SOIC16
IN1 B 2
OUT1 3
IN2 A 4
IN2 B 5
OUT2 6
VSS 7
N.C. 8
CHT-74132 DATCAoSntHacEtE: TGonzalo Picún (+32-10-489214)Jul. 14
16 VDD
15 IN4 A
14 IN4 B
13 OUT4
12 IN3 A
11 IN3 B
10 OUT3
9 N.C.
Pin Symbol Description
1 IN1 A Input A of the NAND gate number 1
2 IN1 B Input B of the NAND gate number 1
3 OUT1 Output of the NAND gate number 1
4 IN2 A Input A of the NAND gate number 2
5 IN2 B Input B of the NAND gate number 2
6 OUT2 Output of the NAND gate number 2
7 VSS Circuit core ground terminal.
8 NC
Not connected
9 NC
Not connected
10 OUT3 Output of the NAND gate number 3
11 IN3 B Input B of the NAND gate number 3
12 IN3 A Input A of the NAND gate number 3
13 OUT4 Output of the NAND gate number 4
14 IN4 B Input B of the NAND gate number 4
15 IN4 A Input A of the NAND gate number 4
16 VDD
Circuit core power supply terminal.
Function Table
A
L
L
H
H
INPUT
B
L
H
L
H
Function and Logical Diagrams
OUTPUT
Y
H
H
H
L
IN1 A
IN1 B
IN2 A
IN2 B
IN3 A
IN3 B
IN4 A
IN4 B
OUT1
OUT2
OUT3
OUT4
A
B
Y
Figure 1. CHT-74132: simplified block diagram.
PUBLIC
Doc. DS-080294 V3.7
WWW.CISSOID.COM
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