S-R Latch. TC74HC279AP Datasheet
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
Quad S -R Latch
The TC74HC279A is a high speed CMOS QUAD S-R LATCH
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
Each latch has an independent Q output and Set and Reset
inputs. S and R are active low. When S input is low, the Q
output goes high and when R input is low, the Q output goes
low. When both S and R are low, S takes precedence
resulting Q = low. When both of S and R are held high, Q
output doesn’t change.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
• High speed: tpd = 12 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 2 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 6 V
• Pin and function compatible with 74LS279
: 1.00 g (typ.)
: 0.18 g (typ.)
Start of commercial production
IEC Logic Symbol
4R (14) R
1 (4) 1Q
2 (7) 2Q
3 (9) 3Q
4 (13) 4Q
Qn: The level of Q before the indicated input condition were established.
#: For latches with doubles S input.
H = Both S input high
L = One of both inputs low
Absolute Maximum Ratings (Note 1)
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC VCC/ground current
−0.5 to 7
−0.5 to VCC + 0.5
−0.5 to VCC + 0.5
500 (DIP) (Note 2)/180 (SOP)
−65 to 150
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be
applied until 300 mW.
Operating Ranges (Note)
Input rise and fall time
2 to 6
0 to VCC
0 to VCC
−40 to 85
0 to 1000 (VCC = 2.0 V)
0 to 500 (VCC = 4.5 V)
0 to 400 (VCC = 6.0 V)
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.