CLOCK CONVERTER. LS7082N1 Datasheet

LS7082N1 CONVERTER. Datasheet pdf. Equivalent

LS7082N1 Datasheet
Recommendation LS7082N1 Datasheet
Part LS7082N1
Description QUADRATURE CLOCK CONVERTER
Feature LS7082N1; LSI/CSI LS7082N1 U® L A3800 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 .
Manufacture LSI
Datasheet
Download LS7082N1 Datasheet




LSI LS7082N1
LSI/CSI
LS7082N1
U® L
A3800 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
QUADRATURE CLOCK CONVERTER
June 2015
FEATURES:
• x1, x2 and x4 mode selection
• Up to 16MHz output clock frequency
• INDEX input and output
• UP/DOWN indicator output
• Programmable output clock pulse width
• On-chip filtering of inputs for optical or
magnetic encoder applications.
• TTL and CMOS compatible I/Os
• +3V to +12V operation (VDD - VSS)
LS7082N1 (DIP); LS7082N1-S (SOIC ) - See Figure 1
DESCRIPTION:
The LS7082N1 is a CMOS quadrature clock converter. Quad-
rature clocks derived from optical or magnetic encoders, when
applied to the A and B Inputs of the LS7082N1, are converted
to strings of Up Clocks and Down Clocks. Pulses derived from
the Index Track of an encoder, when applied to the INDX input,
produce absolute position reference pulses which are syn-
chronized to the Up Clocks and Down Clocks. These outputs
can be interfaced directly with standard Up/Down counters for
direction and position sensing of the encoder.
PIN ASSIGNMENT - TOP VIEW
V DD (+V ) 1
INDX 2
RBIAS 3
V SS (-V ) 4
A5
NC 6
NC 7
FIGURE 1
14 INDX
13 UPCK
12 DNCK
11 UP/DN
10 x4/x1
9B
8 x2
TABLE 1. MODE SELECTION TRUTH TABLE
INPUT/OUTPUT DESCRIPTION:
VDD (Pin 1)
Supply Voltage positive terminal.
x2 Input
0
1
1
x4/x1 Input
0 or 1
0
1
MODE
x2
x1
x4
INDX (Pin 2)
Encoder Index pulses are applied to this input.
RBIAS (Pin 3)
Input for external component connection. A resistor con-
nected between this input and VSS adjusts the output clock
pulse width (Tow). For proper operation, the output clock
pulse width must be less than or equal to the A, B pulse
separation (TOW TPS).
x4/x1 (Pin 10)
This input selects between x1 and x4 modes of operation.
See Table 1 for Mode Selection Truth Table and Figure 2 for
Input/Output timing relationship.
UP/DN (Pin 11)
The count direction at any instant is indicated at this output.
An UP count direction is indicated by a high, and a DOWN
count direction is indicated by a low (See Figure 2).
VSS (Pin 4)
Supply Voltage negative terminal.
A (Pin 5)
Quadrature Clock Input A. This input has a filter circuit to
validate input logic level and eliminate encoder dither.
x2 (Pin 8)
A low level applied to this input selects x2 mode of opera-
tion. See Table 1 for Mode Selection Truth Table and
Figure 2 for Input/Output timing relationship.
B (Pin 9)
Quadrature Clock Input B. This input has a filter circuit
identical to input A.
7082N1-062315-1
DNCK (Pin 12)
This DOWN Clock output consists of low-going pulses gen-
erated when A input lags the B input (See Figure 2).
UPCK (Pin 13)
This UP Clock output consists of low-going pulses gener-
ated when A input leads the B input (See Figure 2).
INDX (Pin 14)
This output consists of low-going pulses generated by a
positive clock transition at the A input when INDX input
is high and B input is low and a negative clock transition
at the B input when INDX input is high and A input is high.
(See Figure 2).
NOTE: All unused input pins must be tied to VDD or VSS.



LSI LS7082N1
ABSOLUTE MAXIMUM RATINGS:
PARAMETER
SYMBOL
VALUE
UNITS
DC Supply Voltage
Voltage at any input
Operating temperature
Storage temperature
VDD - VSS
VIN
TA
TSTG
DC ELECTRICAL CHARACTERISTICS:
PARAMETER
SYMBOL
16 V
VSS-0.3 to VDD+0.3
V
-20 to +85
ºC
-55 to 150
ºC
(Unless otherwise specified VDD = 3V to 12V and TA = -20ºC to +85ºC)
MIN TYP MAX UNITS
CONDITION
Supply Voltage
Supply Current
x4 / x1N: Logic 0
Logic 1
Logic 0 Input Current
Logic 1 Input Current
x2N / INDX: Logic 0
Logic 1
Input Current
A,B INPUTS: Logic 0
Logic 1
Input Current
RBIAS INPUT:
VDD
IDD
Vx4l
Vx4h
Ix4l
Ix4l
Ix4l
Ix4h
Ix4h
Ix4h
Vindxl
Vindxh
Iindxlk
VABl
VABh
IABlk
3 - 12 V
-
- 1.5 1.65 mA VDD = 12V, all input frequencies=0 Hz and RBIAS = 2MΩ
- - 0.5 V
-
VDD - 0.5
-
-
V
- 2.2 4.2 μA
- 3.5 6.9 μA
VDD = 3V
VDD = 5V
- 8.3 16.2 μA
- -2 -9.8 μA
- -3.4 -6.6 μA
- -8.2 -16 μA
- - 0.3*VDD V
VDD = 12V
VDD = 3V
VDD = 5V
VDD = 12V
-
0.7*VDD
-
-
V
- 0 10 nA
-
-
0.7*VDD
- 0.25*VDD V
- -V
-
-
- 0 10 nA
-
External Resistor
ALL OUTPUTS:
RB 2K - 10M Ω
-
Sink Current
Source Current
Iol - -3.2 - mA
Iol - -4.8 - mA
Iol - -7.2 - mA
Ioh - 1.7 - mA
Ioh - 2.2 - mA
Ioh - 3.1 - mA
TRANSIENT CHARACTERISTICS (TA = -20ºC to +85ºC)
PARAMETER
SYMBOL
MIN
TYP
MAX UNITS
CONDITION
Output Clock Pulse Width
A,B INPUTS:
TOW
TOW
TOW
540
180
60
ns VDD = 3V
ns VDD = 5V
ns VDD = 12V
Validation Delay
Phase Delay
Pulse Width
Frequency
Input to output Delay
TVD - 450 -
TVD - 200 -
TVD - 90 -
TPS TVD+TOW
s
TPW
2TPS
-
s
fA,B -
1/(2TPW)
Hz
TDS
-
490 565
ns
VDD = 3V
VDD = 5V
VDD = 12V
-
-
-
VDD = 3V
TDS
-
220 345
ns
VDD = 5V
7082N10623152
TDS
-
125 135
ns
VDD = 12V



LSI LS7082N1
A
B
INDX
UPCK (x1 )
DNCK (x1 )
UPCK (x2 )
DNCK (x2 )
UPCK (x4 )
DNCK (x4 )
INDX
UP/DN
TPW
TPS
TDS
Tow
TDS
FIGURE 2. LS7082N1 INPUT/OUTPUT TIMING DIAGRAM
RBIAS 3
CURRENT
MIRROR
A5
B9
INDX 2
x4/x1 10
x2 8
VDD 1
V SS 4
FILTER
FILTER
+V
-V
DUAL
ONE-SHOT
DUAL
ONE-SHOT
CLOCK
AND
DIRECTION
DECODE
x2 CLOCK
MUX
FIGURE 3. LS7082N1 BLOCK DIAGRAM
14 INDX
11 UP/DN
13
12
7082N1-043009-3







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