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CY7C12771KV18
1.8 V synchronous pipelined SRAM
Description
CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ 36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36) ■ 550 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Doub...
Cypress Semiconductor
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CY7C12771KV18
1.8 V synchronous pipelined SRAM
- Cypress Semiconductor
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