CY7C1305BV25 CY7C1307BV25
18-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture
Features
Functional Description
Separate independent Read and Write data ports Supports concurrent transactions 167-MHz clock for high bandwidth 2.5 ns Clock-to-Valid access time 4-Word Burst for reducing the address bus frequency Double Data Rate (DDR) interfa...
