9FGU0431 Datasheet: 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator





9FGU0431 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator Datasheet

Part Number 9FGU0431
Description 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
Manufacture IDT
Total Page 15 Pages
PDF Download Download 9FGU0431 Datasheet PDF

Features: 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator 9FGU0431 DATASHEET Description The 9FGU0431 is a member of IDT's 1.5V Ultr a-Low-Power PCIe clock family. The devi ce has 4 output enables for clock manag ement, 2 different spread spectrum leve ls in addition to spread off and 2 sele ctable SMBus addresses. Recommended App lication 1.5V PCIe Gen1-2-3 Clock Gener ator Output Features • 4 - 100MHz Low -Power (LP) HCSL DIF pair • 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) s upport Key Specifications • DIF cycle -to-cycle jitter <50ps • DIF output-t o-output skew <50ps • DIF phase jitte r is PCIe Gen1-2-3 compliant • REF ph ase jitter is < 3.0ps RMS Block Diagram Features/Benefits • LP-HCSL outputs ; save 8 resistors compared to standard PCIe device • 39mW typical power con sumption; reduced thermal concerns • OE# pins; support DIF power management • Programmable Slew rate for each out put; allows tuning for various line len gths • Programmable output amplitude; allows tuning for vario.

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4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
9FGU0431
DATASHEET
Description
The 9FGU0431 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family. The device has 4 output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Clock Generator
Output Features
4 - 100MHz Low-Power (LP) HCSL DIF pair
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Block Diagram
Features/Benefits
LP-HCSL outputs; save 8 resistors compared to standard
PCIe device
39mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5 mm VFQFPN; minimal board
space
XIN/CLKIN_25
X2
vOE(3:0)#
OSC
REF1.5
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
DIF3
DIF2
DIF1
DIF0
9FGU0431 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.

                    
                    






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