9FGU0831 Datasheet: 8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator





9FGU0831 8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator Datasheet

Part Number 9FGU0831
Description 8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9FGU0831 Datasheet PDF

Features: 8-O/P 1.5V PCIe Gen 1-2-3 Clock Generato r 9FGU0831 DATASHEET General Descript ion The 9FGU0831 is a member of IDT's 1 .5V Ultra-Low-Power PCIe clock family. The device has 8 output enables for clo ck management, 2 different spread spect rum levels in addition to spread off an d 2 selectable SMBus addresses. Recomme nded Application • 1.5V PCIe Gen1-2-3 Clock Generator Output Features • 8 - 100MHz Low-Power (LP) HCSL DIF pairs • 1 - 1.5V LVCMOS REF output w/Wake-O n-LAN (WOL) support Key Specification DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew < 60ps • DI F phase jitter is PCIe Gen1-2-3 complia nt • REF phase jitter is < 3.0ps RMS Functional Block Diagram Features/Bene fits • LP-HCSL outputs; save 16 resis tors compared to standard PCIe devices • 50mW typical power consumption; red uced thermal concerns • Outputs can o ptionally be supplied from any voltage between 1.05 and 1.5V; maximum power sa vings • OE# pins; support DIF power management • Programmab.

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8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator 9FGU0831
DATASHEET
General Description
The 9FGU0831 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family. The device has 8 output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Clock Generator
Output Features
8 - 100MHz Low-Power (LP) HCSL DIF pairs
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specification
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 60ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Functional Block Diagram
Features/Benefits
LP-HCSL outputs; save 16 resistors compared to standard
PCIe devices
50mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line length
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EM
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6 mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.5
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGU0831 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.

                    
                    






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