9FGV0241 Data Sheet PDF | IDT





(Datasheet) 9FGV0241 PDF Download

Part Number 9FGV0241
Description 2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9FGV0241 Datasheet PDF

Features: 2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CL OCK GENERATOR DATASHEET 9FGV0241 Desc ription The 9FGV0241 is a 2-output very low power frequency generator for PCIe Gen 1, 2 and 3 applications with integ rated output terminations providing Zo= 100. The device has 2 output enables for clock management and supports 2 di fferent spread spectrum levels in addit ion to spread off. Recommended Applicat ion PCIe Gen1/2/3 clock generator Outpu t Features • 2 - 0.7V low-power HCSL- compatible (LP-HCSL) DIF pairs w/Zo=100  • 1 - 1.8V LVCMOS REF output w/Wa ke-On-LAN (WOL) support Key Specificati ons • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps DIF phase jitter is PCIe Gen1-2-3 com pliant • REF phase jitter is <1.5ps R MS Features/Benefits • Integrated te rminations provide 100 differential Zo; reduced component count and board s pace • 1.8V operation; reduced power consumption • OE# pins; support DIF p ower management • LP-HCSL differential clock outputs; reduced.

Keywords: 9FGV0241, datasheet, pdf, IDT, 2-OUTPUT, VERY, LOW, POWER, PCIE, GEN1/2/3, CLOCK, GENERATOR, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

9FGV0241 datasheet
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
DATASHEET
9FGV0241
Description
The 9FGV0241 is a 2-output very low power frequency
generator for PCIe Gen 1, 2, 3 and 4 applications with
integrated output terminations providing Zo=100. The
device has 2 output enables for clock management and
supports 2 different spread spectrum levels in addition to
spread off.
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
2 – 0.7V low-power HCSL-compatible (LP-HCSL) DIF
pairs w/Zo=100
1 – 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3-4 compliant
REF phase jitter is <1.5ps RMS
Features/Benefits
Integrated terminations provide 100differential Zo;
reduced component count and board space
1.8V operation; reduced power consumption
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable Slew rate for each output; allows tuning
for various line lengths
Programmable output amplitude; allows tuning for
various application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 24-pin 4x4 mm VFQFPN; minimal board
space
Block Diagram
vOE(1:0)#
XIN/CLKIN_25
IDT 603-25-150JA4C or
603-25-150JA4I 25MHz
X2
2
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
SSC Capable
PLL
REF
DIF1
DIF0
IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
1
9FGV0241
JUNE 22, 2017

9FGV0241 datasheet   9FGV0241 datasheet   9FGV0241 datasheet   9FGV0241 datasheet   9FGV0241 datasheet   9FGV0241 datasheet   9FGV0241 datasheet  
9FGV0241 datasheet   9FGV0241 datasheet   9FGV0241 datasheet   9FGV0241 datasheet   9FGV0241 datasheet   9FGV0241 datasheet   9FGV0241 datasheet  






Index : 0  1  2  3   4  5  6  7   8  9  A  B   C  D  E  F   G  H  I  J   K  L  M  N   O  P  Q  R   S  T  U  V   W  X  Y  Z
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)