9DB1904B Datasheet | 19 Output Differential Buffer





9DB1904B PDF File (Datasheet) Download

Part Number 9DB1904B
Description 19 Output Differential Buffer
Manufacture IDT
Total Page 18 Pages
PDF Download Download 9DB1904B PDF File

Features: Datasheet 19 Output Differential Buffer for PCIe Gen2 and QPI 9DB1904B Descr iption The 9DB1904 is electrically comp atible to the Intel DB1900GS Differenti al Buffer Specification.This buffer pro vides 19 output clocks for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential clock from a CK410B+ ma in clock generator, such as the ICS932S 421 drives the 9DB1904. The 9DB1904 can provide outputs up to 400MHz in Bypass Mode. Recommended Application 19 Outpu t Differential Buffer for PCIe Gen2 and QPI Key Specifications • DIF output cycle-to-cycle jitter < 50ps • DIF ou tput-to-output skew < 150ps across all outputs Features/Benefits • Power up default is all outputs in 1:1 mode/No SMBus programming • Spread spectrum c ompatible/EMI reductions • Supports o utput frequencies up to 400 MHz in bypa ss mode/flexible fanout buffer • 8 Se lectable SMBus addresses/no SMBus segme ntation required • SMBus address dete rmines PLL or Bypass mode/pin savings • Dedicated VDDA and CK.

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Datasheet
19 Output Differential Buffer for PCIe Gen2 and QPI
9DB1904B
Description
The 9DB1904 is electrically compatible to the Intel DB1900GS
Differential Buffer Specification.This buffer provides 19 output clocks
for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential
clock from a CK410B+ main clock generator, such as the
ICS932S421 drives the 9DB1904. The 9DB1904 can provide
outputs up to 400MHz in Bypass Mode.
Recommended Application
19 Output Differential Buffer for PCIe Gen2 and QPI
Key Specifications
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 150ps across all outputs
Features/Benefits
• Power up default is all outputs in 1:1 mode/No SMBus
programming
• Spread spectrum compatible/EMI reductions
• Supports output frequencies up to 400 MHz in bypass
mode/flexible fanout buffer
• 8 Selectable SMBus addresses/no SMBus
segmentation required
• SMBus address determines PLL or Bypass mode/pin
savings
• Dedicated VDDA and CKPWRGD_PD# pins/easy board
design
Functionality at Power Up (PLL Mode)
100M_133M#
CLK_IN
MHz
1 100MHz
0 133MHz
Pin Configuration
DIF_(18:0)
MHz
CLK_IN
CLK_IN
Power Down Functionality
INPUTS
CKPWRGD_ CLK_IN/
PD#
CLK_IN#
1 Running
0X
OUTPUTS
DIF/DIF#
Running
Hi-Z
PLL State
ON
OFF
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
IREF 1
GNDA 2
VDDA 3
HIGH_BW# 4
100M_133M#_LV 5
DIF_0 6
DIF_0# 7
DIF_1 8
DIF_1# 9
GND 10
9DB1904BKLF
VDD 11
DIF_2 12
DIF_2# 13
DIF_3 14
DIF_3# 15
DIF_4 16
DIF_4# 17
OE_01234# 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54 OE14#
53 DIF_13#
52 DIF_13
51 OE13#
50 DIF_12#
49 DIF_12
48 OE12#
47 VDD
46 GND
45 DIF_11#
44 DIF_11
43 OE11#
42 DIF_10#
41 DIF_10
40 OE10#
39 DIF_9#
38 DIF_9
37 OE9#
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1
1607C —04/19/11

                    
                    






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