9DB433 Datasheet: FOUR OUTPUT DIFFERENTIAL BUFFER





9DB433 FOUR OUTPUT DIFFERENTIAL BUFFER Datasheet

Part Number 9DB433
Description FOUR OUTPUT DIFFERENTIAL BUFFER
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DB433 Datasheet PDF

Features: FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 DATASHEET 9DB433 General De scription The 9DB433 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB433 is driven by a di fferential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. Recommended Applicatio n 4 output PCIe Gen1,2,3 zero-delay/fan out buffer Key Specifications • Outpu t cycle-cycle jitter <50ps • Output t o Output skew <50ps • Phase jitter: P CIe Gen3 <1.0ps rms Functional Block D iagram OE(6,1)# 2 Features/Benefits • 3 Selectable SMBus Addresses; Mulit ple devices can share the same SMBus Se gment • OE# pins; Suitable for Expres s Card applications • PLL or bypass m ode; PLL can dejitter incoming clock Selectable PLL bandwidth; minimizes j itter peaking in downstream PLL's • S pread Spectrum Compatible; tracks sprea ding input clock for low EMI • SMBus Interface; unused outputs can be disabled • Supports undriven.

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FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3
DATASHEET
9DB433
Description
The 9DB433 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB433 is driven by a differential
SRC output pair from an IDT 932S421 or 932SQ420 or
equivalent main clock generator.
Typical Applications
4 output PCIe Gen1–3 zero-delay/fanout buffer
Key Specifications
Output cycle-cycle jitter <50ps
Output to Output skew <50ps
Phase jitter: PCIe Gen3 <1.0ps rms
Block Diagram
OE(6,1)#
2
Features
3 selectable SMBus addresses; multiple devices can
share the same SMBus segment
OE# pins; suitable for Express Card applications
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLLs
Spread spectrum compatible; tracks spreading input
clock for low EMI
SMBus interface; unused outputs can be disabled
Supports undriven differential outputs in Power Down
mode for power management
Output Features
4 0.7V current-mode differential HCSL output pairs
Supports zero delay buffer mode and fanout mode
Selectable bandwidth
50–110MHz operation in PLL mode
5–166MHz operation in Bypass mode
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
STOP
LOGIC
4
DIF(6,5,2,1)
PD#
BYP#_LOBW_HIBW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT® FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3
1
9DB433
MAY 25, 2018

                    
                    






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