9DB633 Data Sheet PDF | IDT





(Datasheet) 9DB633 PDF Download

Part Number 9DB633
Description Six Output Differential Buffer
Manufacture IDT
Total Page 14 Pages
PDF Download Download 9DB633 Datasheet PDF

Features: DATASHEET Six Output Differential Buffe r for PCIe Gen3 9DB633 Recommended Ap plication: 6 output PCIe Gen3 zero-dela y/fanout buffer General Description: Th e 9DB633 zero-delay buffer supports PCI e Gen3 requirements, while being backwa rds compatible to PCIe Gen2 and Gen1. T he 9DB633 is driven by a differential S RC output pair from an IDT 932S421 or 9 32SQ420 or equivalent main clock genera tor. It attenuates jitter on the input clock and has a selectable PLL bandwidt h to maximize performance in systems wi th or without Spread-Spectrum clocking. An SMBus interface allows control of t he PLL bandwidth and bypass options, wh ile 2 clock request (OE#) pins make the 9DB633 suitable for Express Card appli cations. Features/Benefits: • OE# pi ns/Suitable for Express Card applicatio ns • PLL or bypass mode/PLL can dejit ter incoming clock • Selectable PLL b andwidth/minimizes jitter peaking in do wnstream PLL's • Spread Spectrum Comp atible/tracks spreading input clock for low EMI • SMBus Inter.

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9DB633 datasheet
DATASHEET
Six Output Differential Buffer for PCIe Gen3
9DB633
Recommended Application:
6 output PCIe Gen3 zero-delay/fanout buffer
General Description:
The 9DB633 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB633 is driven by a differential SRC
output pair from an IDT 932S421 or 932SQ420 or equivalent
main clock generator. It attenuates jitter on the input clock
and has a selectable PLL bandwidth to maximize
performance in systems with or without Spread-Spectrum
clocking. An SMBus interface allows control of the PLL
bandwidth and bypass options, while 2 clock request (OE#)
pins make the 9DB633 suitable for Express Card
applications.
Features/Benefits:
• OE# pins/Suitable for Express Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input
clock for low EMI
• SMBus Interface/unused outputs can be disabled
Output Features:
• 6 - 0.7V current mode differential HCSL output pairs
Key Specifications:
• Cycle-to-cycle jitter < 50 ps
• Output-to-output skew < 50 ps
• PCIe Gen3 phase jitter < 1.0ps RMS
Block Diagram
OE1#
OE4#
SRC_IN
SRC_IN#
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
DIF1
DIF4
DIF(0,2,3,5)
IREF
IDT® Six Output Differential Buffer for PCIe Gen3
1
1668C—04/20/11

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