9DBV0641 Datasheet: 6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB





9DBV0641 6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB Datasheet

Part Number 9DBV0641
Description 6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBV0641 Datasheet PDF

Features: 6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB w/Zo=10 0ohms 9DBV0641 DATASHEET Description The 9DBV0641 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. It ha s integrated output terminations provid ing Zo=100ohms for direct connection to 100ohm transmission lines. The device has 6 output enables for clock manageme nt and 3 selectable SMBus addresses. Re commended Application 1.8V PCIe Gen1-2- 3 Zero Delay/Fanout Buffer (ZDB/FOB) Ou tput Features • 6 - 1-200 MHz Low-Pow er (LP) HCSL DIF pairs w/Zo=100 Key Specifications • DIF cycle-to-cycle j itter <50ps • DIF output-to-output sk ew <50ps • DIF phase jitter is PCIe G en1-2-3 compliant • DIF additive phas e jitter <300fs rms for SGMII Block Dia gram Features/Benefits • Direct conn ection to 100ohm transmission lines; sa ves 24 resistors compared to standard P CIe devices • 55mW typical power cons umption in PLL mode; minimal power cons umption • Outputs can optionally be s upplied from any voltage between 1.05 and 1.8V; maximum power s.

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6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBV0641
DATASHEET
Description
The 9DBV0641 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. It has integrated output terminations
providing Zo=100ohms for direct connection to 100ohm
transmission lines. The device has 6 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF additive phase jitter <300fs rms for SGMII
Block Diagram
Features/Benefits
Direct connection to 100ohm transmission lines; saves 24
resistors compared to standard PCIe devices
55mW typical power consumption in PLL mode; minimal
power consumption
Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(5:0)#
6
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0641 REVISION D 04/28/16 1 ©2016 Integrated Device Technology, Inc.

                    
                    






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